55 lines
4.1 KiB
Markdown
55 lines
4.1 KiB
Markdown
# re-BBA-RB — PCB Layout Checklist / Floor-Plan Plan
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Board: ~40 × 100 mm, **1.2 mm, 4-layer, ENIG**. Interposer is a break-off tab of the same panel.
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## 1. Stackup (1.2 mm 4-layer)
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- **L1 SIG** · **L2 GND (GC_Ground)** · **L3 PWR (3V3)** · **L4 SIG** — ground image plane directly under the top-side parts.
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- Thin prepreg on L1–L2 and L3–L4; thick core L2–L3 (so PWR↔GND plane cap is weak → lean on discrete decoupling).
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- On L2, the ground plane carries **GC_Ground** everywhere **except a `USB_GND` island** in the isolated corner.
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- Put the cleanest/fastest GC-referenced nets (EXI, Ethernet pairs) on **L1 over L2 GND**; slower/tolerant nets on L4.
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## 2. Isolation barrier (the #1 rule)
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- One continuous **gap on all four layers** separating the floating section from the board. **Zero signals cross it** — only U5 (ADuM4160) and U6 (ADuM5000) bridge it, internally.
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- **Floating section** (put together in one corner, over the L2 `USB_GND` island): J1 (USB-C), D1 (USBLC6), U4 (AP2112K floating LDO), primary sides of U5/U6.
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- Cross-barrier parts: **R8 (1 MΩ)** + **C18 (1 nF Y-cap)** — place C18 hard across the gap, short loop.
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- USB-C **CC Rd resistors R6/R7** present; keep near the connector.
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## 3. isoPower (U6 ADuM5000) EMI — 180 MHz radiator
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- Keep the isolated island **small**; solid ground under U6.
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- Bypass **C60/C61 (0.1 µF)** right at VDD1/VISO; the 10 µF bulk (C16/C18 on the rail) near U6 too.
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- Keep U6 **away from the W5100 PHY, the Ethernet magnetics, and the USB/EXI signal lines**.
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- Optional (only if chasing compliance): **overlapping-plane stitching** — extend L1 GC_Ground over the L2 USB_GND across the gap (vias to GND only on the GC side; no vias in the overlap). Otherwise the discrete C18 handles the 180 MHz fundamental.
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## 4. Buck (U3 TPS562201) — hot loop
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- **C3 ∥ C60 (2× 10 µF, input)** tight to VIN with a short, wide return — this is the hot loop.
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- **L1 (2.2 µH)** and **C9 ∥ C10 (2× 22 µF, output)** close; keep the **SWN** copper small (min area, no sensitive traces near it).
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- **C4 (bootstrap)** right at SW/VBST. Feedback divider **R1/R2** away from SWN, FB trace short.
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- **C59 (100 µF electrolytic, 12 V bulk)** at the EXI 12 V entry; **C5** decoupling near VIN.
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## 5. W5100S (U11) + Ethernet
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- **Y2 (25 MHz) + C57/C58 (10 pF, CL=8 pF)** hard against XI/XO, guard with ground.
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- **R16 (RSET 12.4 k)** close to RSET_BG; **FB3 (120R, 1 A) + C56 (3.3 µF)** on the 1V2O→1V2A/D path, short and low-DCR.
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- **TX/RX differential pairs → magjack (J2):** short, **100 Ω differential**, matched length, over solid GC_Ground; keep the two pairs apart. Center-tap caps + terminations close.
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- LED resistors **R14/R15 (330)** near the magjack LEDs.
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- **Load switch U12** on the W5100 3.3 V feed, enabled by `GC_ON`; place at the W5100 power entry.
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## 6. FT2232H (U8) + USB
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- **Y1 (12 MHz) + C24/C25 (18 pF)** at OSCI/OSCO — verify frequency at bring-up, tune caps if off.
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- **FB1/FB2 (600R) + C27/C28** on VPHY/VPLL, close to the pins; **C22+R9** reset RC near RESET#; **R10 (12 k)** on REF.
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- **USB D+/D−:** floating side (J1↔U5) on **L1 over USB_GND**; board side (U5↔U8) on **L4 over GC_Ground**. ~90 Ω diff (full-speed via ADuM4160, so forgiving) but keep references clean.
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## 7. iCE40 (U9) + support
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- Decoupling (C36/C37/C40/C41/C46/C47 etc.) one per VCC pin, tight.
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- **VCCPLL filter R13 (100) + C43/C45** right at VCCPLL; **U1 (1V2 LDO) + C39/C42/C44** near the core.
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- **X1 (12 MHz osc) + C80** near the clock input pin; **U10 (SPI flash)** close to the config pins.
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## 8. EXI / SP1 interposer (J3)
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- EXI signals (CLK/CS/MOSI/MISO/INT) reference **GC_Ground continuously** to the edge fingers.
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- **EXTIN → 10 k (R18) → SP1_3V3**; the 12 V bulk near the connector.
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- Interposer: **1.2 mm, ENIG, edge chamfer** on the gold fingers; **break-off tab on a different edge** than the fingers.
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## 9. General
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- Every decoupling cap next to its pin (values/positions already specced in the schematic).
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- Via-stitch the two ground pours generously; via-fence the isolated island edge.
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- Confirm before order: **X1 package**, **SP1 footprint geometry**, magjack/USB-C footprints vs datasheets.
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