Roflin
7587636b48
bba_devid fails on a console with 00 04 02 02 -- the ID correct but one byte
late -- and it fails in its REAL shape, with the 16 us gap and exactly four
bytes clocked, so this is not the t_raw_id probe artefact. The register suite
passes, so register-space reads are fine; only command space is affected.
Cause is latency, not phase. A command-space header is two bytes, so the
reply must be in the tx FIFO by the LAST RISING EDGE of the header transfer:
one byte time, 296 ns at 27 MHz. The round trip is rx AsyncFIFO (~125 ns) +
a sync cycle + tx AsyncFIFO (~110 ns) = 280-320 ns, marginal by construction.
HEADER0 already pushed in the same cycle it consumed byte 0, so the FSM side
was already as early as it can be.
The inter-transfer gap cannot rescue it: the load happens on that last rising
edge and the clock is PAUSED afterwards, so no edge exists during the gap for
anything to update. That is why bba_devid's 16 us gap makes no difference.
Pre-pushing the ID at CS-fall does not work either -- the engine's
unconditional per-byte pops would eat it, and the header length is not known
until byte 0 has been decoded, which is the latency in question.
So take the round trip out of the path. The device ID is a hardwired constant
and belongs to the physical interface rather than to the register file, and
byte 0 == 0x00 identifies the query exactly (bit 7 clear = command space, bit
6 clear = read, reg 0). SPIMode3Slave now recognises it and answers
04 02 02 00 from the EXI clock domain, with no CDC at all. The only thing it
needs from sync is id_phase, a single bit that changes once, crossed with an
FFSynchronizer.
The register file's ID path is REMOVED rather than kept as a fallback: left
in, it would push bytes that a 2-byte header has too few pops to drain, which
is exactly how an earlier version made the NEXT enumeration come back a slot
late.
Tests follow the responsibility:
- spi_mode3_slave T7: the query returns 04 02 02 00 with the tx FIFO
deliberately feeding 0x00, so only the fast path can be answering.
- spi_mode3_slave T8: and it is GATED -- with id_arm low, 0x5A comes
through from the FIFO. Without this the fast path would hijack address 0
forever and the GC could never read NCRA back after its own reset.
- bba_register_file T1: retargeted to assert the FSM pushes NOTHING for an
ID query, which is the property that stops stale bytes corrupting the
following transaction.
Note what these tests do NOT establish: bba_top already passed the device ID
at EXI_HALF=1 before this change, because simulation cannot reproduce a
296 ns window miss -- the sync domain's latency relative to the EXI clock in
sim does not match silicon closely enough. T7/T8 prove the fast path works;
the evidence that it is NECESSARY is the hardware result plus the paused-clock
argument above.
--seeds 8: clk 28.4-31.0 MHz, EXI 56.7-64.4 MHz, 8/8 PASS. Best seed 2
(clk 30.98, EXI 59.47), flashed.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
419 lines
19 KiB
Python
419 lines
19 KiB
Python
"""SPI Mode 3 byte-oriented slave for the EXI bus — CLOCKED BY EXI CLK.
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CPOL=1, CPHA=1 (real Mode 3): CLK idles HIGH, the master CHANGES MOSI on the
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falling edge and both ends SAMPLE on the rising edge.
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Architecture
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------------
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The engine is clocked by the EXI clock itself rather than oversampling it from
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a faster domain:
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exiclk posedge of EXI CLK — sample MOSI, assemble RX bytes, AND
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launch MISO one bit early (see the TX
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note in elaborate)
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CS_N asynchronous reset
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Why, and what it fixes (hardware 2026-10-03)
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--------------------------------------------
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The previous version oversampled EXI CLK from a 54 MHz `capture` domain, which
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put BIT-level timing across a clock-domain boundary: the engine's view of the
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clock lagged the pin by 2 stages of `FFSynchronizer` plus a register, ~3 ticks
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≈ 55 ns. One EXI bit at 27 MHz is 37 ns, so MISO came out ~2 bits late and the
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master read `0x17` as `05 C0` (= `0x17 >> 2`). Register reads were correct up
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to 4 MHz and failed from 8 MHz — the sweep read `ok=[1,1,1,0,0,0]`.
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No amount of oversampling fixes that: at 54 MHz there are only 2 ticks per bit,
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and the design cannot close the 81 MHz that 3x would need. Clocking the engine
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from the EXI pin makes MISO clock-to-Q instead, and moves the ONLY remaining
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crossing to the byte-level AsyncFIFOs, which have a whole byte-time (~296 ns at
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27 MHz) of slack instead of a fraction of a bit.
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EXI CLK (pin 44) sits at die (6,0) on the 5k-sg48, which is global buffer input
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net 6 — so it can drive a real clock network with no board change.
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The domains are created by the PARENT (`ExiCapture`) so the byte FIFOs can name
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them; this module only uses `m.d.exiclk`.
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"""
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from amaranth import *
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__all__ = ["SPIMode3Slave"]
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class SPIMode3Slave(Elaboratable):
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"""Byte-oriented SPI Mode 3 slave, clocked by the EXI clock.
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Ports
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-----
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spi_clk / spi_mosi / spi_cs_n : raw inputs from the GC. spi_clk drives the
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exiclk domain and spi_cs_n its async reset (both wired by
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the parent); they are still listed here so the module is self-describing
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and so spi_cs_n can gate MISO combinationally.
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spi_miso : output to the GC; idles HIGH while CS is deasserted.
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rx_byte : last complete received byte (valid while rx_valid is high)
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rx_valid : 1-cycle pulse in `exiclk` when rx_byte holds a new byte
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tx_byte : byte to transmit; sampled at each byte boundary
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tx_load : 1-cycle pulse asking upstream for the next byte, one per byte
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boundary. No header-length or slot-threshold logic: see the TX comment
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in elaborate() for why unconditional pops are both sufficient and
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necessary.
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"""
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def __init__(self, phase_meter=False):
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# DIAGNOSTIC: when set, every byte the engine transmits is the constant
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# 0x80 instead of the FIFO head. The load/shift/mux/output path is
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# otherwise untouched, so the register file and both byte FIFOs drop
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# out of the picture and what the host reads back is purely the
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# engine's byte PHASE: 0x80 = aligned, 0x40 = 1 bit late, 0x20 = 2 bits
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# late, and so on. Not a functional build.
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self._phase_meter = phase_meter
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self.spi_clk = Signal(init=1) # idles HIGH
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self.spi_mosi = Signal()
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self.spi_cs_n = Signal(init=1) # active LOW
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self.spi_miso = Signal(init=1)
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# The SAME bit as spi_miso, but combinational from the PRE-edge state,
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# so it can feed an SB_IO output register clocked on the falling edge.
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# Driving MISO from a flop inside the IO block removes the fabric
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# routing between the shift register and the pad, which is what the
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# 27 MHz GameCube read fails on -- see the note in synth.py.
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self.miso_next = Signal(init=1)
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# Asserted while the device-ID query is still answerable (the register
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# file's id_phase, synchronised into this domain by the parent).
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self.id_arm = Signal()
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self.rx_byte = Signal(8)
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self.rx_valid = Signal()
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self.tx_byte = Signal(8)
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self.tx_load = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── RX: sample MOSI on the RISING edge (Mode 3 samples on edge 2) ──
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rx_shift = Signal(8)
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rx_bit = Signal(3)
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nxt = Cat(self.spi_mosi, rx_shift[:-1]) # MSB-first: shift left, new bit at LSB
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m.d.exiclk += rx_shift.eq(nxt)
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m.d.exiclk += rx_bit.eq(rx_bit + 1)
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# rx_byte/rx_valid are COMBINATIONAL, not registered. The clock stops
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# and CS rises immediately after a transaction's final bit, so a
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# registered pulse would need one more clock edge that never arrives
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# and the LAST byte of every transaction would be silently lost
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# (symptom: a 4-byte write landed as DE AD BE 00, and a 34-byte TX
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# stream as 15 bytes). Driving them combinationally makes the FIFO
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# capture the byte on the very edge that completes it.
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m.d.comb += self.rx_byte .eq(nxt)
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m.d.comb += self.rx_valid.eq(rx_bit == 7)
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# ── Device-ID fast path, answered HERE and not by the register file ──
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# A command-space header is only TWO bytes, so a reply that travels
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# rx AsyncFIFO -> sync FSM -> tx AsyncFIFO has one byte time (296 ns
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# at 27 MHz) to make it back. That round trip costs ~280-320 ns, so
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# it is marginal by construction, and measured on a console it LOST:
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# the ID came back one byte late (00 04 02 02). The inter-transfer
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# gap cannot rescue it either -- the reply must be in hand by the last
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# rising edge of the header transfer, and the clock is paused after
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# that edge, so nothing can update during the gap.
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#
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# The device ID is a CONSTANT and belongs to the physical interface
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# rather than to the register file, so answer it from this domain and
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# skip both crossings entirely. byte 0 == 0x00 identifies the query
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# exactly: bit 7 clear = command space, bit 6 clear = read, reg = 0.
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byte_idx = Signal(3) # bytes completed this transaction (saturating)
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id_mode = Signal()
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with m.If(rx_bit == 7):
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with m.If(byte_idx != 7):
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m.d.exiclk += byte_idx.eq(byte_idx + 1)
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with m.If((byte_idx == 0) & (nxt == 0x00) & self.id_arm):
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m.d.exiclk += id_mode.eq(1)
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# Byte N of the reply is loaded at the end of header byte N, so the
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# four ID bytes are selected by byte_idx 1..4.
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id_byte = Signal(8)
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with m.Switch(byte_idx):
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with m.Case(1): m.d.comb += id_byte.eq(0x04)
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with m.Case(2): m.d.comb += id_byte.eq(0x02)
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with m.Case(3): m.d.comb += id_byte.eq(0x02)
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with m.Default(): m.d.comb += id_byte.eq(0x00)
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id_sel = Signal()
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m.d.comb += id_sel.eq(id_mode & (byte_idx >= 1) & (byte_idx <= 4))
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# ── TX: launch MISO a FULL CYCLE EARLY, on the RISING edge ────────
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# The host samples MISO on the rising edge. The obvious thing is to
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# drive it on the preceding FALLING edge, which gives the output path
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# a HALF period -- 18.5 ns at 27 MHz. That is not enough on this
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# part, and the shortfall is irreducible:
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#
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# MISO changes at (falling edge AT THE CONNECTOR)
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# + input pad delay
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# + GLOBAL CLOCK NETWORK INSERTION <-- the big one
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# + IOB clock-to-Q
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# + output pad delay
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# ... and the host still needs its own setup time on top.
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#
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# Measured on a GameCube 2026-10-03 with PHASE_METER=1 (the engine
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# drives a constant 0x80 per byte, so the host reads the engine's byte
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# phase directly, with the register file and both byte FIFOs out of the
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# path). Per-speed dump, first two slots per EXI speed index:
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#
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# 0:8080 1:8080 2:8080 3:8080 4:8080 5:C040
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#
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# Perfect to 16 MHz, one bit late at 27 MHz. An 8-slot dump at 27 MHz
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# read C0 40 40 40 C0 40 40 40 -- a UNIFORM one-bit lag (ones at bit
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# 1, 9, 17, 25, 33, ...), with extra highs at bits 0 and 32 where
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# libogc splits the read into two 4-byte transfers and MISO tri-states
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# to its pull-up in the gap.
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#
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# Crucially, ~9 ns was removed from the fabric output path first (the
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# EXI_J4 pad merge, then the CS mux, then the whole fabric route by
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# moving the output into an SB_IO register) and the result stayed BYTE
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# IDENTICAL. Nine nanoseconds out of an 18.5 ns budget cannot change
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# nothing if propagation delay were the whole story, so the remaining
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# cost is the part no RTL change can touch: getting the clock in and
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# the data back out of the chip.
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#
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# So stop shrinking the delay and DOUBLE THE BUDGET. Present the bit
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# the host will sample at rising edge N on rising edge N-1, giving the
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# whole path a FULL period (37 ns at 27 MHz) instead of half. The
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# output then changes shortly AFTER the edge on which the host samples
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# the previous bit, which is safe in both directions: the insertion
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# delay that caused the problem now covers the host's hold time, and
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# a full period covers its setup.
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#
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# `tx_out` is therefore clocked on the RISING edge and loads at
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# rx_bit == 7 -- one bit-time earlier than a falling-edge shifter
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# loading at rx_bit == 0. init=0xFF parks MISO high under CS reset.
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# This also removes `tx_hold` and the whole exiclk_n domain: the
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# engine now has ONE clock edge and ONE phase reference.
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tx_out = Signal(8, init=0xFF)
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tx_src = Signal(8) # the byte loaded at the next byte boundary
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m.d.comb += tx_src.eq(
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Mux(id_sel, id_byte,
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0x80 if self._phase_meter else self.tx_byte))
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m.d.comb += self.tx_load.eq(rx_bit == 7)
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with m.If(rx_bit == 7):
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m.d.exiclk += tx_out.eq(tx_src)
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with m.Else():
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m.d.exiclk += tx_out.eq(Cat(0, tx_out[:-1]))
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m.d.comb += self.spi_miso.eq(tx_out[7])
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# What tx_out[7] WILL be after the next RISING edge -- this is what the
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# SB_IO output register captures. Mirrors the load/shift choice above
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# exactly; T6 proves the two agree bit for bit.
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m.d.comb += self.miso_next.eq(Mux(rx_bit == 7, tx_src[7], tx_out[6]))
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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class _Harness(Elaboratable):
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"""Wraps the slave with the pin-driven domain its parent normally
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creates, so the engine can be exercised standalone."""
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def __init__(self):
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self.dut = SPIMode3Slave()
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def elaborate(self, platform):
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m = Module()
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m.domains.exiclk = cd_p = ClockDomain(async_reset=True)
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d = self.dut
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m.d.comb += [
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cd_p.clk.eq(d.spi_clk), cd_p.rst.eq(d.spi_cs_n),
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]
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m.submodules.dut = d
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return m
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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HP = Period(MHz=27) / 2 # one EXI half-period at the hardware rate
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top = _Harness()
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dut = top.dut
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failures = []
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def check(name, got, want):
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ok = got == want
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print(f" {'ok ' if ok else 'FAIL'} {name}: got {got}, want {want}")
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if not ok:
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failures.append(name)
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# A STRICT Mode 3 master. Unlike a convenience model that parks MOSI long
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# before the edge, this one changes MOSI exactly ON the falling edge and
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# samples MISO in the CLK-low phase. That is what makes the edge
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# convention observable: a slave that sampled MOSI on the falling edge
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# would capture the previous bit, and one that drove MISO on the rising
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# edge would come out a bit late. Both bugs shipped to hardware against a
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# lax master that could not see them.
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async def spi_byte(ctx, mosi_val, probe_rx=False):
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miso = 0
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rx = None
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for bit in range(7, -1, -1):
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ctx.set(dut.spi_clk, 0) # falling edge
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ctx.set(dut.spi_mosi, (mosi_val >> bit) & 1)
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await ctx.delay(HP)
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miso = (miso << 1) | ctx.get(dut.spi_miso) # sample in CLK-low
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if probe_rx and bit == 0:
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rx = (ctx.get(dut.rx_valid), ctx.get(dut.rx_byte))
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ctx.set(dut.spi_clk, 1) # rising edge: slave samples
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await ctx.delay(HP)
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return (miso, rx) if probe_rx else miso
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async def cs_low(ctx):
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ctx.set(dut.spi_clk, 1)
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ctx.set(dut.spi_cs_n, 0)
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await ctx.delay(HP)
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async def cs_high(ctx):
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP)
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ctx.set(dut.spi_cs_n, 1)
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await ctx.delay(HP * 4)
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async def tb(ctx):
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ctx.set(dut.spi_cs_n, 1)
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ctx.set(dut.spi_clk, 1)
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ctx.set(dut.tx_byte, 0)
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await ctx.delay(HP * 4)
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# T1 — RX samples MOSI on the RISING edge, MSB first.
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# rx_byte/rx_valid are combinational and peak during the final bit,
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# which is the instant the parent's FIFO captures them.
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await cs_low(ctx)
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seen = []
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for b in (0x80, 0x00, 0x31, 0x00):
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_, (valid, byte) = await spi_byte(ctx, b, probe_rx=True)
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seen.append((valid, byte))
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await cs_high(ctx)
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check("T1 rx bytes", [b for _, b in seen], [0x80, 0x00, 0x31, 0x00])
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check("T1 rx_valid", [v for v, _ in seen], [1, 1, 1, 1])
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# T2 — TX: the byte latched at the end of slot N appears in slot N+1,
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# MSB first. Slot 0 is the reset value, before any load.
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await cs_low(ctx)
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ctx.set(dut.tx_byte, 0xA5)
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s0 = await spi_byte(ctx, 0x00)
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ctx.set(dut.tx_byte, 0x3C)
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s1 = await spi_byte(ctx, 0x00)
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ctx.set(dut.tx_byte, 0x00)
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s2 = await spi_byte(ctx, 0x00)
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await cs_high(ctx)
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# Slot 0 is the header byte: the host ignores MISO there and the
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# engine has not loaded anything yet, so it reads the CS-reset parking
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# value (tx_out init=0xFF, which is what keeps MISO high while
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# deselected). The bits the host actually uses start at slot 1.
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check("T2 miso slot0 (pre-load)", hex(s0), hex(0xFF))
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check("T2 miso slot1", hex(s1), hex(0xA5))
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check("T2 miso slot2", hex(s2), hex(0x3C))
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# T3 — tx_load pulses exactly once per byte, during the final bit.
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await cs_low(ctx)
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loads = 0
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for _ in range(3):
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for bit in range(8):
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ctx.set(dut.spi_clk, 0)
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await ctx.delay(HP)
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loads += ctx.get(dut.tx_load)
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP)
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await cs_high(ctx)
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check("T3 tx_load pulses", loads, 3)
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# T4 — MISO releases HIGH when CS is deasserted, so it never fights
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# another EXI device sharing the bus.
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check("T4 miso idles high", ctx.get(dut.spi_miso), 1)
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# T5 — a transaction that BEGINS ON A RISING EDGE. The host asserts
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# CS while CLK is already low, so the first edge the device sees is a
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# rise and the transaction carries one fewer FALLING edge than rising.
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# A TX phase counted on falling edges slips one bit here and never
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# recovers; a phase taken from rx_bit cannot.
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#
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# THIS IS THE HARDWARE BUG. On a GameCube the phase-meter build read
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# 0x20 (= 0x80 >> 2) in every slot, identically at 1 MHz and 27 MHz.
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# Nothing in the old testbench started a transaction this way -- every
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# case asserted CS with CLK high -- so the falling and rising counts
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# always matched and the slip was structurally invisible, exactly as
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# the Mode 2/3 mix-up was invisible to a master that parked MOSI early.
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ctx.set(dut.spi_clk, 0) # CLK already LOW ...
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ctx.set(dut.spi_cs_n, 0) # ... when CS asserts
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await ctx.delay(HP)
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ctx.set(dut.tx_byte, 0xA5)
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await spi_byte(ctx, 0x00) # slot 0: header, MISO don't-care
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ctx.set(dut.tx_byte, 0x3C)
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s1 = await spi_byte(ctx, 0x00)
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s2 = await spi_byte(ctx, 0x00)
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await cs_high(ctx)
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check("T5 rising-edge start, slot1", hex(s1), hex(0xA5))
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check("T5 rising-edge start, slot2", hex(s2), hex(0x3C))
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# T6 — miso_next must equal what spi_miso BECOMES on the next RISING
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# edge. The synthesised build drives the pad from an SB_IO register
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# clocked on that edge (synth.py), so if this ever diverges the
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# hardware and the simulation stop agreeing about MISO -- which is
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# precisely the class of bug that has cost this design the most time.
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ctx.set(dut.spi_clk, 1)
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|
ctx.set(dut.spi_cs_n, 0)
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|
await ctx.delay(HP)
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|
ctx.set(dut.tx_byte, 0x6B)
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|
mismatch = 0
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|
for _ in range(3):
|
|
for _bit in range(8):
|
|
ctx.set(dut.spi_clk, 0)
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|
await ctx.delay(HP)
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|
predicted = ctx.get(dut.miso_next) # before the RISING edge
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|
ctx.set(dut.spi_clk, 1)
|
|
await ctx.delay(HP)
|
|
if ctx.get(dut.spi_miso) != predicted:
|
|
mismatch += 1
|
|
await cs_high(ctx)
|
|
check("T6 miso_next predicts spi_miso", mismatch, 0)
|
|
|
|
# T7 — the device-ID fast path. A command-space query (byte 0 = 0x00,
|
|
# byte 1 = 0x00) must be answered 04 02 02 00 straight from this
|
|
# domain, with the tx FIFO empty: the register file cannot make the
|
|
# round trip inside a 2-byte header's one byte time, which on a
|
|
# console returned the ID one byte late (00 04 02 02).
|
|
ctx.set(dut.id_arm, 1)
|
|
ctx.set(dut.tx_byte, 0x00) # FIFO deliberately contributes nothing
|
|
await cs_low(ctx)
|
|
await spi_byte(ctx, 0x00) # header byte 0 identifies the query
|
|
await spi_byte(ctx, 0x00) # header byte 1
|
|
got = [await spi_byte(ctx, 0x00) for _ in range(4)]
|
|
await cs_high(ctx)
|
|
check("T7 device ID", [hex(b) for b in got],
|
|
[hex(x) for x in (0x04, 0x02, 0x02, 0x00)])
|
|
|
|
# T8 — and it must be GATED. Once the GC's first NCRA reset clears
|
|
# id_phase, address 0 reads back NCRA, so the fast path must stop
|
|
# hijacking the reply and let the FIFO through.
|
|
ctx.set(dut.id_arm, 0)
|
|
ctx.set(dut.tx_byte, 0x5A)
|
|
await cs_low(ctx)
|
|
await spi_byte(ctx, 0x00)
|
|
await spi_byte(ctx, 0x00)
|
|
got2 = [await spi_byte(ctx, 0x00) for _ in range(2)]
|
|
await cs_high(ctx)
|
|
check("T8 fast path gated by id_arm", [hex(b) for b in got2],
|
|
[hex(0x5A), hex(0x5A)])
|
|
|
|
sim = Simulator(top)
|
|
sim.add_testbench(tb)
|
|
with sim.write_vcd("SPIMode3Slave.vcd"):
|
|
sim.run()
|
|
|
|
if failures:
|
|
print("\nFAILURES:")
|
|
for f in failures:
|
|
print(" -", f)
|
|
sys.exit(1)
|
|
print("\nAll tests passed.")
|