Roflin
2458884160
Replaces the invented 2-byte header (addr split across both bytes, 2-bit
length field) with the protocol libogc and Swiss actually speak:
command (bit7=0, 6-bit reg) [reg, 00, 00, data] one 4-byte transfer
register (bit7=1, 16-bit reg) [0x80|w<<6, ah, al, 00] + data until CS
This was not an optimisation: the old decoder read Swiss's NWAYS read
(80 00 31 00) as 'write 0x31 to NCRA', and bit 0 of 0x31 is RESET, so every
register read would have reset the device.
Changes:
* 16-bit address; no length field -- register reads and writes now stream
until CS, like the SPRAM path already did
* RHDR_LO starts the SPRAM fetch as soon as the address completes, using
the trailing header byte as the prefetch window the protocol provides
* command space serves EXI regs 0x02/0x03 (interrupt mask/status), the only
two Swiss uses
* EXI_GetID gets its own path: it offers just ONE header byte of warning, so
the first ID byte is pushed the instant byte 0 identifies the query
Two timing subtleties, both found by simulation and commented in place:
* MISO is driven LIVE from the tx FIFO head, so a byte pushed while the pad
byte is on the wire appears in the pad slot. A filler byte is parked
there (MISO is don't-care through the header) so the first real response
lands in data slot 0.
* the prefetch must be one-shot; re-firing while waiting for the pad byte
consumed the register stream early and shifted reads by a byte.
All testbenches updated to the real format and passing: bba_register_file
(7), bba_top (8 incl. the full W5100->SPRAM->GC loop and TX), exi_j4,
exi_capture, spi_mode3_slave, tx_frame_drain, spram_arbiter,
rx_frame_assembler, w5100_parallel_master. gc_bba_test rebuilt against the
new protocol.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
#include "bba.h"
|
|
#include <string.h>
|
|
#include <unistd.h>
|
|
#include <ogc/lwp_watchdog.h>
|
|
|
|
u32 bba_speed = EXI_SPEED32MHZ; /* nominal name; ~27 MHz in reality */
|
|
u32 bba_gap_us = 16; /* see bba.h -- 0 reproduces the raw failure */
|
|
|
|
/* Busy-wait, not usleep(): we are holding the EXI lock with CS asserted, so
|
|
* yielding here is both unnecessary and imprecise at these timescales. */
|
|
static void gap(void)
|
|
{
|
|
u64 t0;
|
|
if (!bba_gap_us) return;
|
|
t0 = gettime();
|
|
while (ticks_to_microsecs(diff_ticks(t0, gettime())) < bba_gap_us) ;
|
|
}
|
|
|
|
/* Real GC<->BBA protocol (docs/exi_protocol_real.md), verified against libogc
|
|
* and Swiss. Register space is a 4-byte header followed by a data phase that
|
|
* runs until CS -- there is no length field.
|
|
* read [0x80, addr>>8, addr&0xFF, 0x00] + N bytes
|
|
* write [0xC0, addr>>8, addr&0xFF, 0x00] + N bytes
|
|
* The trailing 0x00 is the device's prefetch window: the address completes a
|
|
* whole byte before the data phase so the register file can fetch in time. */
|
|
static int begin(void)
|
|
{
|
|
int tries;
|
|
/* EXI_Lock fails outright (rather than blocking) when another subsystem
|
|
* holds the channel -- Swiss or a libogc driver may have it briefly.
|
|
* Retry for ~100 ms before giving up so a transient collision does not
|
|
* surface as a test failure. */
|
|
for (tries = 0; tries < 100; tries++) {
|
|
if (EXI_Lock(BBA_EXI_CHAN, BBA_EXI_DEV, NULL) > 0) break;
|
|
usleep(1000);
|
|
}
|
|
if (tries == 100) return -1;
|
|
if (EXI_Select(BBA_EXI_CHAN, BBA_EXI_DEV, bba_speed) <= 0) {
|
|
EXI_Unlock(BBA_EXI_CHAN);
|
|
return -2;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void end(void)
|
|
{
|
|
EXI_Deselect(BBA_EXI_CHAN);
|
|
EXI_Unlock(BBA_EXI_CHAN);
|
|
}
|
|
|
|
static int put_hdr(u16 addr, int write)
|
|
{
|
|
u32 h = ((u32)(write ? 0xC0 : 0x80) << 24) | ((u32)addr << 8);
|
|
if (EXI_Imm(BBA_EXI_CHAN, &h, 4, EXI_WRITE, NULL) <= 0) return -3;
|
|
if (EXI_Sync(BBA_EXI_CHAN) <= 0) return -4;
|
|
return 0;
|
|
}
|
|
|
|
int bba_read(u16 addr, void *buf, u32 len)
|
|
{
|
|
int rc;
|
|
if (len < 1) return -10;
|
|
if ((rc = begin()) < 0) return rc;
|
|
if ((rc = put_hdr(addr, 0)) < 0) { end(); return rc; }
|
|
gap();
|
|
memset(buf, 0, len);
|
|
if (EXI_ImmEx(BBA_EXI_CHAN, buf, len, EXI_READ) <= 0) { end(); return -5; }
|
|
end();
|
|
return 0;
|
|
}
|
|
|
|
int bba_write(u16 addr, const void *buf, u32 len)
|
|
{
|
|
int rc;
|
|
u8 tmp[64];
|
|
if (len < 1 || len > sizeof(tmp)) return -10;
|
|
memcpy(tmp, buf, len);
|
|
if ((rc = begin()) < 0) return rc;
|
|
if ((rc = put_hdr(addr, 1)) < 0) { end(); return rc; }
|
|
if (EXI_ImmEx(BBA_EXI_CHAN, tmp, len, EXI_WRITE) <= 0) { end(); return -6; }
|
|
end();
|
|
return 0;
|
|
}
|
|
|
|
int bba_devid(u8 id[4])
|
|
{
|
|
int rc;
|
|
u16 h = 0x0000; /* command space, reg 0, read */
|
|
if ((rc = begin()) < 0) return rc;
|
|
if (EXI_Imm(BBA_EXI_CHAN, &h, 2, EXI_WRITE, NULL) <= 0) { end(); return -3; }
|
|
if (EXI_Sync(BBA_EXI_CHAN) <= 0) { end(); return -4; }
|
|
gap();
|
|
memset(id, 0, 4);
|
|
if (EXI_ImmEx(BBA_EXI_CHAN, id, 4, EXI_READ) <= 0) { end(); return -5; }
|
|
end();
|
|
return 0;
|
|
}
|
|
|
|
int bba_r8(u16 addr)
|
|
{
|
|
u8 v;
|
|
int rc = bba_read(addr, &v, 1);
|
|
return rc < 0 ? rc : (int)v;
|
|
}
|
|
|
|
int bba_w8(u16 addr, u8 val)
|
|
{
|
|
return bba_write(addr, &val, 1);
|
|
}
|
|
|
|
int bba_stream(u16 addr, void *buf, u32 len)
|
|
{
|
|
/* Identical to bba_read now: the real protocol always streams until CS,
|
|
* so there is no separate "DMA" header form. */
|
|
return bba_read(addr, buf, len);
|
|
}
|
|
|
|
int bba_tx_bytes(const u8 *buf, u32 len)
|
|
{
|
|
u32 i;
|
|
for (i = 0; i < len; i++) {
|
|
int rc = bba_w8(REG_TXDATA, buf[i]);
|
|
if (rc < 0) return rc;
|
|
}
|
|
return 0;
|
|
}
|