Dennis Brentjes
122 lines
6.8 KiB
Markdown
122 lines
6.8 KiB
Markdown
# CPL rotation corrections — re-bba-rb
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`re-bba-rb-cpl.csv` is generated from `kicad-cli pcb export pos` (raw KiCad
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rotation values), **then hand-corrected** for the parts below before each
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regeneration. This file exists because that correction step is easy to lose
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silently — regenerating the CPL "the normal way" wipes it out, and there is
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no automated check that would catch that. Read this before touching the CPL.
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## Why this exists
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KiCad's per-footprint rotation is measured from an arbitrary reference baked
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into whoever drew that footprint — it does not reliably match what JLCPCB's
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placement machine expects. This is a well-known, generic problem (see
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`cpl_rotations_db.csv` from the JLCKicadTools / kicad-jlcpcb-tools projects
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for the community's attempt at a fix), but **the generic community
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correction table was tried on this board and found wrong** — it claims
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`LQFP-: 270°`, but on this exact board/toolchain pairing (KiCad 10 +
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`kicad-cli pcb export pos`, not the dedicated plugin) the raw LQFP/QFN
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rotation is already correct. The generic table's values are calibrated
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against that plugin's own raw-rotation baseline, which is not the same
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baseline `kicad-cli`'s raw CSV export produces (different Y-axis handling
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between the two tools). **Do not reapply the community table wholesale to
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this board.** Every correction below was derived per-part from direct visual
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verification against JLCPCB's placement-preview render, not from that table.
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## Rotation sign convention
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The CPL uses JLCPCB's Y-up coordinate frame (`kicad-cli`'s csv pos format
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already negates Y from KiCad's native Y-down). In that frame, **increasing
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rotation angle is counter-clockwise** (standard math convention). So when
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the user reports "needs N degrees clockwise", the correction applied is
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**`new = (old - N) % 360`**, not `+N`. Get this backwards and every fix
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lands 2×N off instead of correct.
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## How the correction was (re-)applied each time
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```python
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import csv
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corrections = { 'REF': degrees, ... } # positive = CCW, negative = CW
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with open('re-bba-rb-cpl.csv', newline='') as f:
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rows = list(csv.DictReader(f))
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for r in rows:
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if r['Designator'] in corrections:
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old = float(r['Rotation'])
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new = (old + corrections[r['Designator']]) % 360
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r['Rotation'] = f"{new:.6f}"
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with open('re-bba-rb-cpl.csv', 'w', newline='') as f:
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writer = csv.DictWriter(f, fieldnames=['Designator','Mid X','Mid Y','Layer','Rotation'])
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writer.writeheader()
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writer.writerows(rows)
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```
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When regenerating the CPL from scratch (e.g. after a reroute or component
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move), **re-run `kicad-cli pcb export pos` for fresh positions, then
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reapply every correction below** — don't just diff/copy the old file, since
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positions can legitimately change while rotations still need the same
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correction offset applied on top.
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## Confirmed correct as-is — apply NO correction
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- **U8, U11 (LQFP-48/64)**, **U9 (QFN-48)** — "all large chips are right"
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(user, direct placement-preview check). Raw KiCad rotation is correct.
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- **U4 (SOT-23-5)** — confirmed good *after* the -90° family correction
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below was applied (net rotation 270°, i.e. raw 0° − 90°).
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- **J2 (HR911105A magjack, rot=90° in the PCB file)** — not a CPL-rotation
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question (J2 doesn't need per-part correction below, it's not in the CPL
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correction set), but its physical orientation was independently verified:
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the RJ45 signal pins (pins 1–8, footprint local +Y) map to absolute −X
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under the board's 90° placement rotation, which correctly faces the
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board's tongue/cable-exit edge. Pin 1 appearing to "face outside the
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board" in the placement render is *expected*, not a defect — the RJ45
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contacts are always near the cable-insertion opening by construction.
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## Corrections applied (all currently in `re-bba-rb-cpl.csv`)
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Each row: designator, package, raw→corrected, confidence.
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| Ref | Package | Raw | Corrected | Confidence |
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|---|---|---|---|---|
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| U7 | SOIC-8 | 90° | **180°** | Reconstructed hypothesis (see below) — not independently re-confirmed |
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| U10 | SOIC-8 | 0° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| D1 | SOT-23-6 | 0° | **270°** | Reconstructed hypothesis — not independently re-confirmed |
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| D4 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| D5 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| U12 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| U1 | SOT-23-5 | 180° | **0°** (two corrections: -90° then another -90°, user-confirmed both times) | **Confirmed** by direct user feedback, twice |
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| Q1 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic) |
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| Q2 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** (same as Q1) |
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| D2 | custom `SON50P110X213X50-7` | 0° | **270°** | **Confirmed** ("90° clockwise") |
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| D3 | `Diode_SMD:D_SMA` | 180° | **0°** | **Confirmed** ("180°", direction-agnostic) |
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| C65 | `Capacitor_SMD:CP_Elec_6.3x7.7` | 0° | **180°** | **Confirmed** ("180°", direction-agnostic) |
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| U2 | SOT-583-8 | 180° | **90°** | **Confirmed** ("90° clockwise") |
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**"Reconstructed hypothesis" parts (U7, U10, D1, D4, D5, U12) explained:**
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the user reported "SOIC and SOT chips are rotated 90°, direction unsure."
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Cross-referencing against *earlier* feedback in the same session — where a
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-90° correction had been applied to the top-layer SOT-23 parts and NOT
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flagged as wrong, while the same -90° applied to a SOIC part (U10) WAS
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flagged wrong — implies SOT-23 needs -90° and SOIC needs the opposite,
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+90°. This is indirect reasoning, not a fresh direct check, and **U1 later
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proved that even within one confirmed-wrong-by-90°-family, the correction
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does NOT reliably generalize per package type** (U1 and U4 are both
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SOT-23-5, both got the -90° family correction, but U1 needed a *second*
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-90° on top while U4 was already correct) — so treat every "reconstructed
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hypothesis" row above as **worth a fresh placement-preview check**, not
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settled fact, despite no contradicting feedback having come in since.
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## Parts never checked at all
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Every 0402/0603/0805 passive (R/C/L), J1/J3/J4 connectors, the custom
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`U3` footprint (`hardware:SOT95P280X110-6N`), and anything else not listed
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above is sitting at **raw, unverified KiCad rotation** in the CPL. Passives
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in symmetric packages are usually fine raw (this matched observed behavior
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for the ones implicitly checked), but this has not been confirmed
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part-by-part the way the table above was.
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## Bottom line for whoever picks this up next
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Before ordering assembly, re-check the *entire* board in JLCPCB's (or
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whatever assembler's) placement preview — this file only covers what's been
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individually verified so far, not a general guarantee the CPL is correct.
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