Roflin
5f7f20db43
Remaining after the bit-phase fix was a SPEED-DEPENDENT failure -- the GC read
correctly at 1/2/4/8/16 MHz and failed only at index 5 (27 MHz), returning
0B 80 = 0x17 late by exactly ONE bit. Opposite signature to the phase slip it
was hiding under, and this one really is propagation delay.
MISO is source-synchronous: driven on the falling edge, sampled by the GC on
the next rising edge, so the whole path must fit a HALF period -- 18.5 ns at
27 MHz -- minus global-buffer insertion, pad, connector and the GC's setup.
The failing build measured ~10.5 ns of that internally. Critical path:
clk-to-q 1.39 tx_shift (3,12)
routing 3.60 tx_shift[7] (3,12) -> (5,5) to the CS mux
logic 1.21 Mux(cs_n, 1, ...) LUT
routing 4.79 miso (5,5) -> (17,0) to the J4 MISO pad
10.99 ns (2.60 logic, 8.39 routing)
Two removals, both of things that were pure cost here:
1. EXI_J4 is GONE entirely (exi_j4.py, the resource, the AND merge, the docs
section, scripts/pi-exi-wirecheck.py) -- recoverable from git history. The
AND put a LUT in the CLOCK path, denying the EXI clock pad its dedicated
global-buffer route, and MISO fanned out to the J4 pad at die (17,0) which
was the far end of the critical output path: 4.79 ns of routing to a header
with nothing plugged into it. 10.2-11.5 ns -> 9.3-9.6 ns.
2. The Mux(cs_n, 1, ...) LUT is gone from the MISO data path. It only parked
MISO high when deselected, which the flop's own reset value does for free:
tx_shift now has init=0xFF and CS is that domain's async reset, so MISO is
tx_shift[7] with nothing in between. Removes 1.21 ns of logic plus the
3.60 ns route feeding it and lets the placer sit the flop by the pad.
synth.py now PARSES AND RANKS BY the MISO clock-to-pad delay. Ranking by fmax
was how a board that failed at 27 MHz passed every seed at >=1.29x margin --
fmax was never the binding constraint for this design.
--seeds 8: clk 28.7-32.5 MHz, EXI 49.6-62.1 MHz, MISO 8.38-10.22 ns, 8/8 PASS.
Best seed 8 (clk 30.35, EXI 49.56, MISO 8.38 ns), flashed.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
320 lines
14 KiB
Python
320 lines
14 KiB
Python
"""SPI Mode 3 byte-oriented slave for the EXI bus — CLOCKED BY EXI CLK.
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CPOL=1, CPHA=1 (real Mode 3): CLK idles HIGH, the master CHANGES MOSI on the
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falling edge and both ends SAMPLE on the rising edge.
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Architecture
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------------
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The engine is clocked by the EXI clock itself rather than oversampling it from
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a faster domain:
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exiclk posedge of EXI CLK — sample MOSI, assemble RX bytes
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exiclk_n negedge of EXI CLK — drive MISO (must change BETWEEN the
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master's sampling edges)
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CS_N asynchronous reset for both
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Why, and what it fixes (hardware 2026-10-03)
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--------------------------------------------
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The previous version oversampled EXI CLK from a 54 MHz `capture` domain, which
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put BIT-level timing across a clock-domain boundary: the engine's view of the
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clock lagged the pin by 2 stages of `FFSynchronizer` plus a register, ~3 ticks
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≈ 55 ns. One EXI bit at 27 MHz is 37 ns, so MISO came out ~2 bits late and the
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master read `0x17` as `05 C0` (= `0x17 >> 2`). Register reads were correct up
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to 4 MHz and failed from 8 MHz — the sweep read `ok=[1,1,1,0,0,0]`.
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No amount of oversampling fixes that: at 54 MHz there are only 2 ticks per bit,
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and the design cannot close the 81 MHz that 3x would need. Clocking the engine
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from the EXI pin makes MISO clock-to-Q instead, and moves the ONLY remaining
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crossing to the byte-level AsyncFIFOs, which have a whole byte-time (~296 ns at
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27 MHz) of slack instead of a fraction of a bit.
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EXI CLK (pin 44) sits at die (6,0) on the 5k-sg48, which is global buffer input
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net 6 — so it can drive a real clock network with no board change.
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The domains are created by the PARENT (`ExiCapture`) so the byte FIFOs can name
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them; this module just uses `m.d.exiclk` / `m.d.exiclk_n`.
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"""
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from amaranth import *
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__all__ = ["SPIMode3Slave"]
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class SPIMode3Slave(Elaboratable):
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"""Byte-oriented SPI Mode 3 slave, clocked by the EXI clock.
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Ports
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-----
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spi_clk / spi_mosi / spi_cs_n : raw inputs from the GC. spi_clk drives the
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exiclk/exiclk_n domains and spi_cs_n their async reset (both wired by
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the parent); they are still listed here so the module is self-describing
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and so spi_cs_n can gate MISO combinationally.
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spi_miso : output to the GC; idles HIGH while CS is deasserted.
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rx_byte : last complete received byte (valid while rx_valid is high)
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rx_valid : 1-cycle pulse in `exiclk` when rx_byte holds a new byte
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tx_byte : byte to transmit; sampled at each byte boundary
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tx_load : 1-cycle pulse asking upstream for the next byte, one per byte
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boundary. No header-length or slot-threshold logic: see the TX comment
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in elaborate() for why unconditional pops are both sufficient and
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necessary.
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"""
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def __init__(self, phase_meter=False):
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# DIAGNOSTIC: when set, every byte the engine transmits is the constant
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# 0x80 instead of the FIFO head. The load/shift/mux/output path is
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# otherwise untouched, so the register file and both byte FIFOs drop
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# out of the picture and what the host reads back is purely the
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# engine's byte PHASE: 0x80 = aligned, 0x40 = 1 bit late, 0x20 = 2 bits
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# late, and so on. Not a functional build.
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self._phase_meter = phase_meter
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self.spi_clk = Signal(init=1) # idles HIGH
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self.spi_mosi = Signal()
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self.spi_cs_n = Signal(init=1) # active LOW
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self.spi_miso = Signal(init=1)
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self.rx_byte = Signal(8)
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self.rx_valid = Signal()
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self.tx_byte = Signal(8)
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self.tx_load = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── RX: sample MOSI on the RISING edge (Mode 3 samples on edge 2) ──
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rx_shift = Signal(8)
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rx_bit = Signal(3)
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nxt = Cat(self.spi_mosi, rx_shift[:-1]) # MSB-first: shift left, new bit at LSB
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m.d.exiclk += rx_shift.eq(nxt)
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m.d.exiclk += rx_bit.eq(rx_bit + 1)
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# rx_byte/rx_valid are COMBINATIONAL, not registered. The clock stops
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# and CS rises immediately after a transaction's final bit, so a
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# registered pulse would need one more clock edge that never arrives
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# and the LAST byte of every transaction would be silently lost
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# (symptom: a 4-byte write landed as DE AD BE 00, and a 34-byte TX
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# stream as 15 bytes). Driving them combinationally makes the FIFO
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# capture the byte on the very edge that completes it.
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m.d.comb += self.rx_byte .eq(nxt)
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m.d.comb += self.rx_valid.eq(rx_bit == 7)
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# ── TX: pop on the POSEDGE, present on the NEGEDGE ────────────────
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# AsyncFIFO needs a posedge clock internally, so the FIFO is read in
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# `exiclk` and the byte is handed to the negedge side through a plain
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# register. posedge -> negedge of the SAME clock is a half-period
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# path (18.5 ns at 27 MHz), which is ample.
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#
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# One pop per byte boundary, unconditionally. The byte popped at the
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# end of byte N is presented during byte N+1, so:
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# - pops during the header drain whatever the previous transaction
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# left in the FIFO (this replaces the old CS-fall flush), and
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# - the response the register file pushes during the protocol's
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# turnaround byte is popped at that byte's end and lands in data
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# slot 0, exactly where it belongs.
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# No header-length or slot-threshold logic is needed at all.
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tx_hold = Signal(8)
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m.d.comb += self.tx_load.eq(rx_bit == 7)
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with m.If(rx_bit == 7):
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m.d.exiclk += tx_hold.eq(0x80 if self._phase_meter else self.tx_byte)
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# MISO must settle on the falling edge, before the master samples it
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# on the rising one. Driving it on the rising edge is one bit late by
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# construction -- that was the 05 C0 bug.
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# The byte phase comes from `rx_bit` -- the RISING-edge counter -- NOT
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# from a free-running falling-edge counter of its own.
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#
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# A separate tx_bit counting falling edges only stays in step with the
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# host while the host emits exactly as many falls as rises. It does
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# not: a transfer that begins on a rising edge (CS asserted while CLK
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# is low, or the clock gating between two of the host's back-to-back
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# transfers) delivers a rise with no matching fall, and tx_bit silently
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# slips one bit behind for the rest of the transaction. RX never
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# notices, because the rising count always equals the host's bit count.
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#
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# Measured on a GameCube 2026-10-03 with a diagnostic build that drives
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# a constant 0x80 per byte (PHASE_METER=1 in synth.py): every slot read
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# back 0x20 = 0x80 >> 2, i.e. the engine was TWO falling edges behind,
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# identically at 1 MHz and at 27 MHz. Speed-independence is the tell —
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# a propagation problem cannot survive a 1000 ns bit time, and an
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# output-edge error would have moved when the edge was flipped (it did
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# not: the rising-edge and falling-edge builds returned byte-identical
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# 05 C0 for a NWAYS read).
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#
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# Slaving the shift register to rx_bit gives the engine ONE phase
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# reference, the same edge the host counts, so the two cannot drift.
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# init=0xFF so CS (the domain's async reset) parks MISO HIGH by
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# itself. MISO is then tx_shift[7] with NOTHING in between -- no
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# Mux(cs_n, 1, ...) LUT in the data path. That mux cost 1.21 ns of
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# logic AND 3.60 ns of routing to reach it, on a source-synchronous
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# output that has only a HALF period (18.5 ns at 27 MHz) to reach the
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# GameCube's sampling edge. Removing it also frees the placer to put
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# this flop next to the MISO pad.
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tx_shift = Signal(8, init=0xFF)
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with m.If(rx_bit == 0):
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m.d.exiclk_n += tx_shift.eq(tx_hold) # byte boundary: load MSB
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with m.Else():
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m.d.exiclk_n += tx_shift.eq(Cat(0, tx_shift[:-1]))
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m.d.comb += self.spi_miso.eq(tx_shift[7])
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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class _Harness(Elaboratable):
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"""Wraps the slave with the two pin-driven domains its parent normally
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creates, so the engine can be exercised standalone."""
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def __init__(self):
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self.dut = SPIMode3Slave()
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def elaborate(self, platform):
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m = Module()
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m.domains.exiclk = cd_p = ClockDomain(async_reset=True)
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m.domains.exiclk_n = cd_n = ClockDomain(async_reset=True,
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clk_edge="neg")
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d = self.dut
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m.d.comb += [
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cd_p.clk.eq(d.spi_clk), cd_p.rst.eq(d.spi_cs_n),
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cd_n.clk.eq(d.spi_clk), cd_n.rst.eq(d.spi_cs_n),
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]
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m.submodules.dut = d
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return m
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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HP = Period(MHz=27) / 2 # one EXI half-period at the hardware rate
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top = _Harness()
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dut = top.dut
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failures = []
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def check(name, got, want):
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ok = got == want
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print(f" {'ok ' if ok else 'FAIL'} {name}: got {got}, want {want}")
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if not ok:
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failures.append(name)
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# A STRICT Mode 3 master. Unlike a convenience model that parks MOSI long
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# before the edge, this one changes MOSI exactly ON the falling edge and
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# samples MISO in the CLK-low phase. That is what makes the edge
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# convention observable: a slave that sampled MOSI on the falling edge
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# would capture the previous bit, and one that drove MISO on the rising
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# edge would come out a bit late. Both bugs shipped to hardware against a
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# lax master that could not see them.
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async def spi_byte(ctx, mosi_val, probe_rx=False):
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miso = 0
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rx = None
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for bit in range(7, -1, -1):
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ctx.set(dut.spi_clk, 0) # falling edge
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ctx.set(dut.spi_mosi, (mosi_val >> bit) & 1)
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await ctx.delay(HP)
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miso = (miso << 1) | ctx.get(dut.spi_miso) # sample in CLK-low
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if probe_rx and bit == 0:
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rx = (ctx.get(dut.rx_valid), ctx.get(dut.rx_byte))
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ctx.set(dut.spi_clk, 1) # rising edge: slave samples
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await ctx.delay(HP)
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return (miso, rx) if probe_rx else miso
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async def cs_low(ctx):
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ctx.set(dut.spi_clk, 1)
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ctx.set(dut.spi_cs_n, 0)
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await ctx.delay(HP)
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async def cs_high(ctx):
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP)
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ctx.set(dut.spi_cs_n, 1)
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await ctx.delay(HP * 4)
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async def tb(ctx):
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ctx.set(dut.spi_cs_n, 1)
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ctx.set(dut.spi_clk, 1)
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ctx.set(dut.tx_byte, 0)
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await ctx.delay(HP * 4)
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# T1 — RX samples MOSI on the RISING edge, MSB first.
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# rx_byte/rx_valid are combinational and peak during the final bit,
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# which is the instant the parent's FIFO captures them.
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await cs_low(ctx)
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seen = []
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for b in (0x80, 0x00, 0x31, 0x00):
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_, (valid, byte) = await spi_byte(ctx, b, probe_rx=True)
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seen.append((valid, byte))
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await cs_high(ctx)
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check("T1 rx bytes", [b for _, b in seen], [0x80, 0x00, 0x31, 0x00])
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check("T1 rx_valid", [v for v, _ in seen], [1, 1, 1, 1])
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# T2 — TX: the byte latched at the end of slot N appears in slot N+1,
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# MSB first. Slot 0 is the reset value, before any load.
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await cs_low(ctx)
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ctx.set(dut.tx_byte, 0xA5)
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s0 = await spi_byte(ctx, 0x00)
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ctx.set(dut.tx_byte, 0x3C)
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s1 = await spi_byte(ctx, 0x00)
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ctx.set(dut.tx_byte, 0x00)
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s2 = await spi_byte(ctx, 0x00)
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await cs_high(ctx)
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check("T2 miso slot0 (pre-load)", hex(s0), hex(0x00))
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check("T2 miso slot1", hex(s1), hex(0xA5))
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check("T2 miso slot2", hex(s2), hex(0x3C))
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# T3 — tx_load pulses exactly once per byte, during the final bit.
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await cs_low(ctx)
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loads = 0
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for _ in range(3):
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for bit in range(8):
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ctx.set(dut.spi_clk, 0)
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await ctx.delay(HP)
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loads += ctx.get(dut.tx_load)
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP)
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await cs_high(ctx)
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check("T3 tx_load pulses", loads, 3)
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# T4 — MISO releases HIGH when CS is deasserted, so it never fights
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# another EXI device sharing the bus.
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check("T4 miso idles high", ctx.get(dut.spi_miso), 1)
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# T5 — a transaction that BEGINS ON A RISING EDGE. The host asserts
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# CS while CLK is already low, so the first edge the device sees is a
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# rise and the transaction carries one fewer FALLING edge than rising.
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# A TX phase counted on falling edges slips one bit here and never
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# recovers; a phase taken from rx_bit cannot.
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#
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# THIS IS THE HARDWARE BUG. On a GameCube the phase-meter build read
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# 0x20 (= 0x80 >> 2) in every slot, identically at 1 MHz and 27 MHz.
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# Nothing in the old testbench started a transaction this way -- every
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# case asserted CS with CLK high -- so the falling and rising counts
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# always matched and the slip was structurally invisible, exactly as
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# the Mode 2/3 mix-up was invisible to a master that parked MOSI early.
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ctx.set(dut.spi_clk, 0) # CLK already LOW ...
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ctx.set(dut.spi_cs_n, 0) # ... when CS asserts
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await ctx.delay(HP)
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ctx.set(dut.tx_byte, 0xA5)
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await spi_byte(ctx, 0x00) # slot 0: header, MISO don't-care
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ctx.set(dut.tx_byte, 0x3C)
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s1 = await spi_byte(ctx, 0x00)
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s2 = await spi_byte(ctx, 0x00)
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await cs_high(ctx)
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check("T5 rising-edge start, slot1", hex(s1), hex(0xA5))
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check("T5 rising-edge start, slot2", hex(s2), hex(0x3C))
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sim = Simulator(top)
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sim.add_testbench(tb)
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with sim.write_vcd("SPIMode3Slave.vcd"):
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sim.run()
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if failures:
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print("\nFAILURES:")
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for f in failures:
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print(" -", f)
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sys.exit(1)
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print("\nAll tests passed.")
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