Roflin
7ad03a34ac
308 -> 322 lines, 18% -> 13% comment-only, and the clock-domain comment was
flatly wrong. It said:
"Two edges are needed: Mode 3 samples MOSI on the RISING edge and MISO
must change on the FALLING edge, between the master's sampling points.
Each edge gets TWO domains with the same clock: *_rst async-reset by
CS ... (plain) no reset ..."
None of that describes this module. There are THREE domains, not four; they
are all the same edge, not two; there is no `*_rst` naming; and MISO has not
changed on the falling edge since the full-cycle-early launch. The docstring
now states what is actually built and, for each domain, what forces its reset
choice: the engine must see CS because its counters restart per transaction,
the FIFO sides must not (resetting one side desynchronises an AsyncFIFO's gray
pointers), and both FIFO sides must be posedge because AsyncFIFO instantiates
a posedge-only reset CDC internally.
Also corrected: "capture domain" and "core domain" in the class docstring,
which are names from the deleted oversampling design; cs_active described as
living in "the exi domain" when it is produced in sync; and a claim that the
engine "hands the byte to its negedge output stage", which no longer exists.
The id_arm comment kept its rule and lost its history: armed permanently
because real hardware answers EXI_GetID whenever asked, and a device that
stops identifying itself reads to the host as ABSENT rather than broken; the
port survives only for the PHASE_METER build.
Structure: elaborate() is now _clock_domains, _bit_engine, _byte_fifos and
_transaction_framing. _transaction_framing records what is deliberately NOT
synchronised here, since that is the non-obvious part -- CLK is a clock and CS
is an async reset, and synchronising them was the original bug rather than a
safety measure.
VERIFIED EQUIVALENT: generated RTLIL identical for both build variants
(phase_meter False and True, 2120 and 2117 lines) after stripping \src
attributes. Full module suite passes and bba_top T9 is 6/6 at EXI_HALF=1, 2
and 8.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>