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Dennis Brentjes 7d7ab34bff Fixes review comments.
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re-bba-rb hardware review — coverage record

Purpose of this file: a complete log of what has been reviewed and how, so a future session/agent does not re-do (or re-litigate) this work. Open action items live in TODO.md; this file records coverage and verdicts, including everything that was checked and found correct.

Maintenance rule (binding): whenever a reviewed circuit is changed, or a new review/verification is performed, update the relevant section here in the same commit. If you change something listed as "verified correct", its entry here must be re-verified or marked stale. TODO.md tracks what to do; REVIEW.md tracks what has been established.

Review window: 2026-07-17 … 2026-07-18. Reviewed by Claude (sessions with Dennis), commits 4704dfb…d0426b3. Verification tooling: kicad-cli 10.0.4 netlist/ERC/DRC/BOM exports, ad-hoc netlist parsers (pins.py/nets.py — parse the kicadxml netlist into per-component pin→net tables; recreate trivially), PDF datasheet extraction, WebSearch/WebFetch for parts and reference designs.

1. Sources reviewed against

Source Where Used for
TPS562201, TPS2116, TPS22810, AP2112K, FT2232H, 93LC46B, USBLC6-2SC6, W5100S, iCE40UP5K, W25Q32JV, MC-711-H72, PUSB3AB6 datasheets datasheets/ (restored from LFS; TPS22810 + PUSB3AB6 added from web) pin functions, abs max, app circuits
WIZnet W5100S reference schematic V1.1.0 (signal.com.tr mirror) fetched, read as image entire MDI/magnetics section, notes 1–7
SD Gecko wiring table (gc-forever wiki), SD2SP2-Pro schematic (github), SP1ETH (github), ETH2GC (github), webhdx IDE-EXI v2 thread (gc-forever t=4843) fetched SP1 DO/DI direction, 12 V rail viability
iceprog source (YosysHQ/icestorm/iceprog/iceprog.c) fetched FTDI pin convention
JLCPCB/LCSC part pages fetched per part every C-number claimed below

2. Power sheet (Power.kicad_sch) — FULLY REVIEWED, PASS

  • TPS562201 (U3, 12V→GC_3V3 buck): EN tied to 12 V checked against abs max — legal (VIN/EN max 19 V). VFB ref 0.768 V; 33k/10k divider → 3.30 V, matches DS Table 7-2 (33.2k/10k). L1 3.3 µH = recommended typ; 2×22 µF out within 20–68 µF window; VBST 100 nF pin-to-SW; input 2×10 µF+100 nF. All per datasheet. Do not re-flag EN-at-12V.
  • TPS2116 (U2, GC/USB 3V3 mux): MODE tied to VIN1 = priority mode (checked truth table); ST = open-drain "low when VIN1 not used" → GC_ON high on GC power, R5 10k pull-up to 3V3 — polarity correct for U12-EN + FPGA-GC_ON use. USB-only fallback verified via truth table (MODE≤0.35 V row). PR1 divider was marginal (1.10 V vs VREF 1.0±8 %) → fixed: R3=150k (switchover 2.30–2.70 V). Abs max (6 V) fine.
  • AP2112K-1.2 (U1) / AP2112K-3.3 (U4): 1 µF X5R in/out present (DS requirement), 600 mA rating vs load fine, dropout headroom checked (1.2 V version has 1.0–1.3 V dropout — OK from 3.3 V), EN=VIN OK.
  • TPS22810 (U12, ETH_3V3 switch): EN never floats (GC_ON has R5 pull-up); QOD floating = valid config; CT floating deliberately accepted — DS Table 2: rise ~98 µs at VIN=3.3 V even with CT=0 → ~0.5 A inrush into ~15 µF; a CT cap changes nothing at 3.3 V. Closed — do not re-open.
  • 12 V input: D3 SMAJ12A orientation/standoff correct; C65 100 µF is a 25 V SMD electrolytic (Lelon VZH101M1ETR-0607 — not THT, assembly OK); C3/C4 25 V, C6 50 V — ratings verified in BOM.
  • 12 V rail viability: verified against webhdx IDE-EXI v2 / M.2 Loader ("3.3V@2A from 12V rail", gc-forever t=4843) — a shipping SP1 product runs the same architecture at higher load. Only remaining bench check: inrush into C65 at GC power-on (expected non-issue).

3. USB sheet (Usb Connector.kicad_sch) — FULLY REVIEWED, PASS after fixes

  • USB-C (J1, MC-711-H72): CC1/CC2 with individual 5.1k pull-downs (correct UFP), A/B pairs tied, VBUS caps 10µ+1µ+100n, shield to GND. PASS.
  • USBLC6 (D1): in-line on D+/D−, pass-through orientation correct (the historic D+/D− swap was fixed in an earlier session; verified again), VBUS pin on USB_VBUS. PASS.
  • FT2232H (U8): all power pins verified against DS pin table — VPHY/VPLL are +3.3 V pins (fed 3V3 via FB1/FB2 + 100 nF — CORRECT; an earlier review note claiming they should be 1.8 V was wrong; do not "fix"). VREGIN=3V3, VREGOUT→VCORE (1.8 V) with 4.7 µF + 3×100 nF on pins 12/37/64; 4×VCCIO decoupled; REF = 12k 1 % to GND (DS requirement); RESET RC (10k/100 nF); 12 MHz crystal Y1 (CL=12 pF part vs 18 pF caps — re-verified 2026-07-31 against the real YXC datasheet + LCSC page; correct, do not change); TEST→GND, AGND→GND.
  • EEPROM 93LC46B (U7): interface was wrong (DO+DI both direct to EEDATA) → fixed per DS Table 3.4: EE_DO net, R30 2.2k (C25879) to EE_DATA, R31 10k (C25744) pull-up to 3V3, DI direct. 93LC46B = fixed 16-bit org = correct for FT2232H. Verified in netlist.
  • EE_CS pull-down (R43, 10 kΩ) — ADDED 2026-07-31. FT2232H DS Table 3.4 states EECS/EECLK/EEDATA are all "Tri-State during device reset", so CS floats while the FT2232H is in reset. The Microchip 93LC46B DS is explicit: "an external 10 kΩ pull-down protection resistor should be added to the CS pin", and CS is active-HIGH ("A high level selects the device; a low level deselects the device and forces it into Standby mode"). It must be a pull-DOWN — a pull-UP would hold the EEPROM permanently selected. Netlist verified: EE_CS: R43.1, U7.1, U8.63.
  • EE_CLK deliberately has NO pull resistor — do not add one. With CS held low the device is in Standby, and the 93LC46B DS states "Before a Start condition is detected, CS, CLK and DI may change in any combination… without resulting in any device operation." A floating clock is harmless once CS is pulled down. (A reviewer suggested pull-ups on both EE_CLK and EE_CS; only the CS pull-DOWN is correct.)
  • FT2232H oscillator needs no RExt / no external feedback resistor — settled, do not add one. DS Figure 6.5 shows crystal + 2 caps only; FTDI publishes no gm, no drive-level and no negative-resistance figure, so a drive resistor cannot be sized from their data and their reference does not use one (feedback is internal). This is a genuine architectural difference from the W5100S, which explicitly has no internal feedback resistor and models RExt in its Figure 23. Y1 caps stay 18 pF (CL=12 pF part).
  • FTDI↔flash/FPGA config pins: rewired 2026-07-18 to stock iceprog convention: SCK=ADBUS0, MOSI=ADBUS1, MISO=ADBUS2, FLASH_CS=ADBUS4, CDONE=ADBUS6, CRESET=ADBUS7 (verified against iceprog.c; old ADBUS3/ACBUS0/ ACBUS1 now NC). R11/R12 10k pull-ups on CRESET/CDONE intact.
  • EEPROM contents decision: ship blank (default 0403:6010 = what iceprog opens). Documented in TODO.

4. FPGA sheet (Fpga.kicad_sch) — FULLY REVIEWED, PASS

  • iCE40UP5K (U9, 4 units): VCC=1V2 (pins 5/30); VCCIO_0/2 + SPI_VCCIO1 = 3V3, each decoupled; VPP_2V5 on 3V3 (standard practice, iCEbreaker does the same); VCCPLL via 100 Ω + 100 nF + 10 nF (Lattice filter); CDONE/CRESET 10k pull-ups; EP→GND.
  • SPI flash (U10 W25Q32JVSS): on the hard-SPI pins (14–17), WP/HOLD 10k pull-ups, shared correctly with FT2232 ADBUS0-2/4 (FTDI Hi-Z at reset; FPGA held in CRESET during FTDI flashing — iCEbreaker-equivalent arrangement).
  • Clocks: X1 12 MHz oscillator → CLK12 on pin 20 (G3 global); EXI_CLK on pin 44 (G6 global). Both verified good pin choices.
  • Pin map (authoritative, incl. 2026-07-18 debug additions): EXI_MOSI=4 (in), EXI_MISO=3 (out), EXI_CLK=44, EXI_CS=45, EXI_INT=46, ETH bus=23–43, CLK12=20, GC_ON=21, ETH_RST=2, UART FPGA-RX=18/TX=19 (net names are FTDI-perspective!), LED_G=47, LED_R=48, DBG0–4=9/10/11/12/6.
  • Debug provisions added 2026-07-18: D6/D7 LEDs + R37/R38, J4 header, TP1/2/4/5 (TP3 on ethernet sheet). Netlist-verified (LED polarity, TPs on global rails, not sheet-local orphans).

5. Ethernet sheet (ethernet.kicad_sch) — FULLY REVIEWED, PASS after fixes

  • W5100S straps/pins, all verified against DS pin table: MOD[3:0]=0100 = "010X" parallel bus ✓; SCLK→GND = documented requirement for bus mode ✓; pin 32=MOSI/A0, pin 33=MISO/A1 (matches WIZnet ref) ✓; CSn/RDn/WRn internal pull-ups (IU), DAT0-7 IOU ✓; INTn is push-pull (type OP) — no pull-up needed, do not add one ✓; RSTn is plain input (type IP) → R36 10k to ETH_3V3 added 2026-07-18.

  • 1V2 loop: 1V2O → C61 4.7 µF → FB3 100 Ω ferrite → 1V2A+1V2D with 5×100 nF — matches ref topology. 3V3A/3V3D common (ref's inter-rail ferrites are marked optional; single-net accepted).

  • RSET_BG: 12.4k 1 % — DS says 12.3k; ACCEPTED (E192 value, WIZnet ref itself uses 12k+300R; 0.8 % immaterial). Closed.

  • Crystal Y2: 25 MHz, CL=12 pF part (C9006) vs 18 pF caps → CL≈12 pF ✓ (DS Table 9 wants 12 pF); mandatory external 1 MΩ feedback (R17) present ✓ (DS: "W5100S has no feedback resistor"). The caps are CORRECT: both crystals are CL = 12 pF, and CL = C/2 + Cstray → 18 pF caps deliver exactly 12 pF. An attempt on 2026-07-31 to "fix" the caps to 30 pF/10 pF was a regression against this reviewed item and has been reverted. Do not change the crystal caps. The trigger for that mistake was wrong CL metadata in the schematic symbol properties (Y1 said 18 pF, Y2 said 8 pF) — those properties have now been corrected to match the parts (see below).

    ⚠️ Where the CL = 12 pF figure actually comes from — read this before "re-verifying" it. It is NOT in datasheets/Ysx321SL.pdf. That is the generic YSX321SL series datasheet and its Load Capacitance row reads "10pF, 20pF, or specify" — so opening it and looking for 12 pF gives the alarming impression that the fitted caps are wrong for either standard option. These two parts are the "or specify" variants, and CL is fixed by the ordering code, confirmed on the LCSC part pages (re-confirmed 2026-07-31):

    • Y1 X322512MOB4SI (C70565): 12 MHz, CL 12 pF, ±10 ppm, ESR 80 Ω
    • Y2 X322525MOB4SI (C9006): 25 MHz, CL 12 pF, ±10 ppm, ESR 50 Ω Everything else in the series datasheet does corroborate the review numbers used elsewhere in this file: C0 = 3 pF max, DL = 200 µW max (100 µW typ — the basis for the R44 RExt decision), and the ESR bands (12–15 MHz → 80 Ω, 16–31 MHz → 50 Ω). Only CL needs the part page.

    The common way to get this wrong is to apply C = 2 × CL = 24 pF and conclude 18 pF is too small. That omits stray capacitance. The correct form is C = 2 × (CL − Cstray) = 2 × (12 − 3) = 18 pF, where Cstray (PCB trace + oscillator pin capacitance) is ~3 pF. If a reviewer says the caps are low, check whether they subtracted Cstray before re-opening this.

    Residual sensitivity (the real uncertainty, and it is acceptable): the match is exact only if Cstray is exactly 3 pF; the realistic range is 2–5 pF, giving CL_actual 11–14 pF against the rated 12 pF. Pulling with C0 = 3 pF and motional C1 ≈ 6 fF works out to roughly +14 ppm to −24 ppm. Against 100BASE-TX's ±100 ppm requirement on the 25 MHz reference, the worst-case stack (±10 tolerance + ±20 temp + ±3/yr aging + ±24 load) is ~±60 ppm — inside spec with margin. For Y1 the FT2232H's USB budget (±500 ppm high-speed, ±2500 ppm full-speed) is met by a wide margin. No change warranted; measure at bring-up if convenient.

  • RExt on XTAL_O (R44, 49.9 Ω) — ADDED 2026-07-31, reverses the earlier "no series RExt (ref uses 0 Ω) — accepted" decision. New evidence that was not available at the original review: the crystal datasheet only entered the repo on 2026-07-31 and rates the part at DL = 200 µW max (100 µW typ), whereas W5100S Table 9 tells you to select a crystal rated 500 µW — i.e. the fitted crystal can be overdriven ~2.5× by the chip. RExt is the datasheet's own prescribed remedy ("RExt: Resistor for limiting the drive level (DL)… Excess power can destroy the crystal") and is modelled in DS Figure 23. Topology follows Figure 23 exactly — RF (R17) across the chip pins XSCI↔XSCO, RExt between XSCO and the crystal/CL2 node; this required splitting the old XTAL_O net, so U11 pin 11 now sits on a new XSCO net: XTAL_I : C62(CL1), R17(RF), U11.12, Y2.1 XSCO : R17(RF), R44(RExt), U11.11 XTAL_O : C63(CL2), R44(RExt), Y2.3 Value 49.9 Ω chosen from the DS gain-margin formula with the REAL specs (F=25 MHz, ESR=50 Ω per the 16–31 MHz band, C0=3 pF max, CL=12 pF, gm=16.7 mA/V): margin 7.53×, against a DS requirement of ≥5 (the "6.99 dB" in Table 8 is 10·log₁₀5). Ceiling is 100 Ω — 120 Ω already fails the startup spec. Fitted value is a starting point; part fields are intentionally blank so it is re-selected/confirmed at bring-up by measuring drive level.

  • Crystal symbol properties corrected 2026-07-31 (they were metadata-only errors, no copper impact, but they caused the regression above): Y1 CL 18 pF→12 pF, ESR 50 Ω→80 Ω (DS band 12–15 MHz), tol ±30 ppm→±10 ppm; Y2 CL 8 pF→12 pF, C0 7 pF→3 pF, ESR 30 Ω→50 Ω (band 16–31 MHz), tol ±50 ppm→±10 ppm.

  • Known deviation, accepted: W5100S DS Table 8 specifies a CL = 8 pF crystal (revision history logs "Modified Load capacitance value (12p → 8p)"), while Table 9 still says 12 pF and was never updated. The fitted part is 12 pF, matching Table 9. Frequency accuracy is unaffected (the crystal sees exactly its rated load, so no pulling error); the only cost is gain margin, which is 7.75× with R44 — well clear of the ≥5 requirement. Accepted; do not re-flag without bench evidence.

  • MDI section — now implements the WIZnet ref schematic item-for-item: 49.9 Ω×4 (R26–R29, C25120) + 100 nF×2 (C18/C19) termination on the PHY-side nets; 3.3 Ω×4 series dampers (R32–R35, C137986) — chain per line: U11 pin → termination tap → 3.3 Ω → ESD → transformer; C20 100 nF + C21 1 µF center-tap bypass at J2 pins 4/5. Net naming: PHY_* (chip side) / MDI_* (damper→ESD) / ETH_* (ESD→jack); all three groups are in the ETH_DP netclass (patterns in re-bba-rb.kicad_pro).

  • D4/D5 (USBLC6 on the pairs) — SETTLED, do not re-litigate: keep. ST rates USBLC6 for Ethernet; 2.5–3.5 pF OK at 100BASE-TX. Two deliberate details: (1) pin 5 floats on purpose (lines are 3.3 V-biased and swing above it; a tied rail would clip peaks; floating rail self-biases and the 6 V zener still clamps); (2) split nets force flow-through routing (pins 1↔6/3↔4 are one internal node) — never merge the nets or stub the diode. Full reasoning in TODO.md.

  • Magjack J2 (HR911105A): transformer spec verified vs DS Table 11 (1:1, 350 µH) ✓; LED wiring (R14/R15 330 Ω anodes to ETH_3V3, cathodes to LNKn/ACTn pins 17/20) — assumed internal LED pinout 9/12=anodes, 10/11=cathodes: confirm at bring-up (no HR911105A datasheet in repo). Pin 8 (Bob-Smith common) + shield tied directly to GND — deviation from ref's 1 nF/2 kV chassis split, accepted deliberately (GC floats, no earth).

  • Ethernet layout (PCB) — reviewed twice (after rework + after insertion): termination 1–3 mm from U11 MDI pins; dampers in-line, MDI stubs 1.45–1.48 mm; D4/D5 flow-through confirmed pad-by-pad; pair skew TX 0.66 mm / RX 1.81 mm (fine at 100M — do not "improve"); pairs on F.Cu over solid In1 GND, one B.Cu crossover via per N line at the jack; In1 plane correctly voided under the magjack cable/isolation side (deliberate, keep); C20/C21 against the jack pin column (as close as the plane void allows); 30 GND stitch vias in the corner; RX pair passes ~3–4 mm from Y2 (accepted, don't move closer); RSET_BG 2.8 mm with one via to B.Cu (plane-shielded, OK).

6. EXI sheet (exi.kicad_sch) — FULLY REVIEWED, PASS after DO/DI fix

  • DO/DI direction — SETTLED with hardware evidence, do not re-litigate: YAGCD SP1 naming is console-perspective: pin 6 DO = GC data out = adapter MOSI input; pin 9 DI = GC data in = adapter MISO output. Evidence: SD Gecko straight-through table (MC pin 5 "DO" → SD CMD input, pin 7 "DI" → SD DAT0 output) + SD2SP2 (DO → OR gate → CMD). The board was wired backwards (following a wrong table in docs/gc_bba_fpga_design.md, since corrected); fixed as a pure rename + R21/R25 identity swap, zero copper changes. Final: J3.6(DO)→R21 22 Ω→FPGA pin 4 = EXI_MOSI; J3.9(DI)→R25 33 Ω→FPGA pin 3 = EXI_MISO.
  • PUSB3AB6 (D2): pinout verified vs Nexperia DS (1=CH1, 2=GND any-pin, 3–7=CH2–6); DFN2111-7 matches the SON50P110X213X50-7 footprint; 0.15 pF/ch; rated for 3.3 V lines. Note: BOM part C49383400 is the ElecSuper clone ("(ES)"), pin-compatible — bring-up suspect only if ESD behaviour odd.
  • EXTIN: 10k (R18) to SP1_3V3 (the GC's own rail) — correct, doesn't back-power. 12 V: J3.5 → 12V_RAW → U13 eFuse → 12V_EXI (see next bullet; was a straight J3.5→12V_EXI connection before 2026-07-31). J3.8 (second 3.3 V pin) deliberately NC. Series elements: R24 100 Ω on EXI_CLK (input damping), R21/R25 as above. INT (J3.3) driven by FPGA pin 46 — gateware should use open-drain emulation (TODO).
  • 12 V inrush limiter (U13, TPS25961 eFuse) — ADDED 2026-07-31 to protect the GameCube's 12 V supply from the surge charging C65+C3+C4+C6 (120 µF) at plug-in/power-on. Topology (netlist-verified): 12V_RAW : J3.5, D3(TVS), C66(Cin 100nF), R46, U13.6 IN 12V_EXI : U13.1 OUT, C65, C3, C4, C6, U3.3 VIN, U3.5 EN EFUSE_EN : R46, R47, U13.5 EN/UVLO EFUSE_ILIM: R45, U13.3 ILIM GND : U13.2 OVLO, U13.4 GND, R45.2, R47.2, C66.2 D3 (SMAJ12A TVS) stays on the INPUT side on purpose — it clamps GC-side surges before they reach the eFuse's 21 V absolute maximum. C65 is on the OUTPUT side on purpose — it is the bulk cap whose inrush we are rate-limiting; moving it upstream would defeat the whole circuit. U3 (buck) needed no change: because the eFuse was inserted upstream of the existing 12V_EXI net name, U3's VIN and EN both land on the switched rail automatically.
    • Inrush is set by the device's INTERNAL slew rate, not an external cap. dV/dt = 5.17 V/ms (fixed, typical) ⇒ I = C·dV/dt = 120 µF × 5.17 V/ms = 621 mA over a 2.3 ms ramp. R_ILIM only matters if it is set below that figure.
    • R45 = 100 kΩ ⇒ I_LIM ≈ 500 mA (datasheet Equation 6: R_ILIM = 50000/I_LIM; 100 kΩ is one of TI's own characterised points, 0.516 A typ, ±18% ⇒ 0.42–0.61 A). This both caps inrush at 500 mA and gives 3.8× headroom over the ~130 mA steady-state 12 V draw. 100 kΩ is deliberately inside a valid ON-resistance bin — Table 7-1 forbids 58.8–66.7 kΩ, 111–142 kΩ and 250–500 kΩ; do not "round" R45 into those bands.
    • Startup dissipation is safe: FET energy = ½CV² = 8.65 mJ regardless of ramp rate ⇒ ~3.0 W average over 2.9 ms. Figure 6-31 puts time-to-thermal- shutdown at ~3 W far beyond 100 ms. Steady-state loss is 106 mΩ × 0.13² = 1.8 mW, negligible.
    • R46/R47 = 620 k/100 k ⇒ UVLO on at 8.9 V typ (9.2 V worst case), off at 8.2 V, 16.7 µA leakage. This is deliberately well below 12 V — do not "improve" it upward. Two reasons: (a) the EN/UVLO threshold is specified 1.2–1.28 V, so an ~11.4 V setting has a worst case of 11.78 V and could refuse to start on a healthy console once PSU tolerance is added; (b) more importantly the falling threshold scales with it (91% of rising), and the eFuse pulls 500 mA during the 2.9 ms ramp — at a ~11 V setting a source impedance of only ~1.2 Ω would sag the rail below drop-out mid-ramp, causing retry oscillation that may never complete startup. The 620 k/100 k setting tolerates 3.85 V of sag. If tighter supervision is ever wanted, 680 k/100 k (9.7 V on, 3.2 V sag margin) is the furthest to push it — beyond that use an FPGA-read divider, not the eFuse enable.
    • OVLO tied directly to GND = internal fixed OV threshold. Note the OVLO pin's absolute maximum is only 6.5 V — it must never see the 12 V rail.
    • Thermal pad must connect to the GND plane (datasheet requirement); the chosen footprint is the _ThermalVias variant for this reason.
    • Symbol: no TPS25961 exists in the KiCad libraries (the stock TPS2596xx is an 8-pin SO-8 with a different pinout — do not substitute it), so hardware/TPS25961.kicad_sym was created and registered in sym-lib-table. Footprint Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm_ThermalVias.
  • EXI series-resistor assignment — VERIFIED AGAIN 2026-07-31 against the netlist + gateware pin directions, do not swap. The DO/DI fix above moved the driven line from J3.6 to J3.9, and the R21/R25 identities were swapped to follow it. Confirmed live: EXI_MISO : U9.3 (synth.py dir="o", FPGA drives) -> R25 33 Ω -> J3.9 (DI) EXI_MOSI : J3.6 (DO, GC drives) -> R21 22 Ω -> U9.4 (dir="i", FPGA rx) 33 Ω belongs on MISO because that is the only line this board drives, so it is genuine source termination (33 Ω + ~30 Ω iCE40 output ≈ 60 Ω into a ~50 Ω trace — mildly over-damped, the safe direction for EMI on a short run). 22 Ω belongs on MOSI, where the GC is the driver at the far side of a connector we do not control; source termination is impossible there, so the resistor only limits clamp current and damps at the receiver, a role where the exact value matters much less. Swapping them would under-terminate the one line we actually drive. This is the exact trap a future reader may fall into after seeing the console-perspective DO/DI naming — the values are already on the correct lines.
  • CS deliberately has NO series resistor — known asymmetry, not an oversight. All three of EXI_CLK, EXI_MOSI and EXI_CS are GC-driven inputs, but only CLK (R24 100 Ω) and MOSI (R21 22 Ω) carry damping; J3.10 goes straight to U9.45. CS is essentially static within a transaction (it frames the transfer rather than toggling per bit), so receiver ringing matters far less than on the clock or data lines. Recorded so it is not "fixed" on the assumption it was forgotten; add one only if bring-up shows CS-edge noise.
  • J3 footprint provenance: 12 contacts, 1 mm effective pitch, two staggered depth rows, front side only, fingers to the board edge (the .kicad_dru has a J3 edge-clearance exception for this). Geometry comes from the physical sp1_test_plug iterations — the test-plug project has no reusable footprint to diff (it only carries FFC breakouts). Outline/ protrusion fit remain bench checks.

7. PCB global / JLCPCB — REVIEWED, PASS

  • DRC: 0 errors / 0 unconnected / 0 parity as of each review point (remaining parity items = the 11 debug/fix footprints awaiting placement + 3 FTDI reroutes + R3 value sync — all listed by F8). Warnings are silkscreen cosmetics only (~150; JLC auto-clips).
  • JLC capability floor: encoded as error-severity rules in re-bba-rb.kicad_dru (0.09 mm trace/space, 0.15 mm drill, 0.2 mm hole-to-copper etc.) — passing. Diff-pair impedance rules (USB 90 Ω, ETH 100 Ω) are error-severity and passing; they police PHY_/MDI_/ETH_* and FT_D*/USB_D* via netclass patterns.
  • Stackup: 7628 prepreg 0.2104 mm / 0.6 mm core ≈ 1.14 mm total = JLC04121H-7628 (JLC nominal 1.2 mm, satisfies SP1 slot). Order with ENIG + gold fingers + 45° bevel (copper_finish field says "None" — cosmetic only). Board 102×33.4 mm.
  • Fiducials: FID1–3 placed 2026-07-18 (board-only footprints) at (195, 68.5)/(131, 48)/(163, 44.5) — track-clearance verified after a first placement attempt collided with tracks (caught by DRC).
  • Zones: In1.Cu = single solid GND plane; In2.Cu = 3V3 + ETH_3V3 (priority 1) islands. No other zones.

8. BOM — FULLY AUDITED (netlist-vs-BOM count check passes)

All orderable components carry Footprint+Value+MPN+LCSC+Manufacturer. Deliberate in_bom no: J3 (gold fingers), J4, TP1–5 — the only allowed netlist/BOM delta. Spot-verified on JLC/LCSC: crystals CL=12 pF (C70565/ C9006, Basic), 49.9 Ω C25120, 3.3 Ω C137986 (YAGEO, Extended), 2.2k C25879, 150k C25755, LEDs C72043/C2286 (Basic), 12 V-rail ratings, 1 % tolerances on R1–R4/R10/R16/R26–R38. D2 = ElecSuper clone (see §6).

9. Explicitly NOT reviewed / remaining risk (don't claim coverage)

  • Mechanical fit (outline vs slot, RJ45/USB-C protrusion) — bench only.
  • HR911105A internal LED pinout — assumed, confirm at bring-up.
  • W5100S register map in the gateware — written from memory per CLAUDE.md; confirm at bring-up.
  • Actual power-on behaviour (12 V inrush, mux transitions under load, FT2232+iCE40 enumeration) — bench only.
  • Gateware (board PCF, GC_ON gating, UART crossover, INT drive style, LED/DBG driving) — tracked in TODO, not part of the hardware review.
  • re-bba-rb.kicad_pcb.old.* / .history/ — deleted/ignored, never reviewed for content.

10. Session/history notes an agent may need

  • datasheets/ was once deleted by an errant commit and restored from the local LFS object store; recovery recipe is in the git log of 4704dfb.
  • A stale case-colliding power.kicad_sch was removed (Windows checkout hazard — never add files differing only in case).
  • The SP1 pin table in docs/gc_bba_fpga_design.md was the root cause of the DO/DI swap and has been corrected — trust it now; it carries a "do not swap" note with the evidence.
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