Dennis Brentjes
120 lines
4.5 KiB
Python
120 lines
4.5 KiB
Python
"""IceBreaker (iCE40 UP5K) vendor-backed async FIFO example.
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This module uses Amaranth's `Memory` with separate write/read ports in different
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clock domains. With the icestorm toolchain the memory typically maps to
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`SB_RAM40_4K` block RAMs. The control (full/empty) is implemented with
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gray-pointer logic and two-stage synchronization of opposing pointers.
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Notes:
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- This prefers block RAM for storage (small LUT usage, lower power).
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- The write/read ports are in independent domains; backend maps ports to
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dual-port RAM primitives when available.
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"""
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from amaranth import *
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class Ice40AsyncFIFO(Elaboratable):
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def __init__(self, depth=256, wdomain="src", rdomain="dst"):
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assert depth & (depth - 1) == 0, "depth must be power of two"
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self.depth = depth
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self.aw = (depth - 1).bit_length()
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self.wdomain = wdomain
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self.rdomain = rdomain
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# serial (1-bit) interface
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self.wdata = Signal()
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self.w_en = Signal()
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self.w_full = Signal()
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self.rdata = Signal()
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self.r_en = Signal()
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self.r_valid = Signal()
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self.r_empty = Signal()
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def elaborate(self, platform):
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m = Module()
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# single-bit-wide memory mapped to vendor BRAMs by the backend
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mem = Memory(width=1, depth=self.depth)
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wp = mem.write_port(domain=self.wdomain)
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rp = mem.read_port(domain=self.rdomain, transparent=False)
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m.submodules += wp, rp
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# pointers (aw+1 bits to include wrap bit)
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wbin = Signal(self.aw + 1)
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wgray = Signal(self.aw + 1)
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rbin = Signal(self.aw + 1)
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rgray = Signal(self.aw + 1)
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# sync registers for opposing pointers (two-stage)
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rgray_sync0 = Signal(self.aw + 1)
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rgray_sync1 = Signal(self.aw + 1)
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wgray_sync0 = Signal(self.aw + 1)
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wgray_sync1 = Signal(self.aw + 1)
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# write-side
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with m.Domain(self.wdomain):
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next_wbin = Signal(self.aw + 1)
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next_wgray = Signal(self.aw + 1)
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m.d.comb += next_wbin.eq(wbin + self.w_en)
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m.d.comb += next_wgray.eq(next_wbin ^ (next_wbin >> 1))
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# sync read pointer into write domain
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for i in range(self.aw + 1):
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m.d[self.wdomain] += rgray_sync0[i].eq(rgray[i])
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m.d[self.wdomain] += rgray_sync1[i].eq(rgray_sync0[i])
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# full detection (standard gray-pointer trick)
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top = self.aw
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low_eq = Signal()
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msb_cmp = Signal()
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m.d.comb += low_eq.eq(next_wgray[top - 1:0] == rgray_sync1[top - 1:0])
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m.d.comb += msb_cmp.eq((next_wgray[top] != rgray_sync1[top]) & (next_wgray[top - 1] != rgray_sync1[top - 1]))
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m.d.comb += self.w_full.eq(low_eq & msb_cmp)
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# perform write
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with m.If(self.w_en & ~self.w_full):
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m.d[self.wdomain] += wp.addr.eq(wbin[self.aw - 1:0])
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m.d[self.wdomain] += wp.data.eq(self.wdata)
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m.d[self.wdomain] += wp.en.eq(1)
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m.d[self.wdomain] += wbin.eq(next_wbin)
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m.d[self.wdomain] += wgray.eq(next_wgray)
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with m.Else():
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m.d[self.wdomain] += wp.en.eq(0)
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# read-side
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with m.Domain(self.rdomain):
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next_rbin = Signal(self.aw + 1)
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next_rgray = Signal(self.aw + 1)
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m.d.comb += next_rbin.eq(rbin + self.r_en)
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m.d.comb += next_rgray.eq(next_rbin ^ (next_rbin >> 1))
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# sync write pointer into read domain
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for i in range(self.aw + 1):
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m.d[self.rdomain] += wgray_sync0[i].eq(wgray[i])
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m.d[self.rdomain] += wgray_sync1[i].eq(wgray_sync0[i])
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m.d.comb += self.r_empty.eq(rgray == wgray_sync1)
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with m.If(self.r_en & ~self.r_empty):
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m.d[self.rdomain] += rp.addr.eq(rbin[self.aw - 1:0])
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m.d[self.rdomain] += rp.en.eq(1)
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m.d[self.rdomain] += rbin.eq(next_rbin)
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m.d[self.rdomain] += rgray.eq(next_rgray)
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m.d[self.rdomain] += self.r_valid.eq(1)
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m.d[self.rdomain] += self.rdata.eq(rp.data)
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with m.Else():
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m.d[self.rdomain] += rp.en.eq(0)
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m.d[self.rdomain] += self.r_valid.eq(0)
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return m
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if __name__ == "__main__":
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# Quick smoke-check: instantiate and print fragment
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from amaranth.back import verilog
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fifo = Ice40AsyncFIFO(depth=256)
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print(verilog.convert(fifo, ports=[fifo.wdata, fifo.w_en, fifo.w_full, fifo.rdata, fifo.r_en, fifo.r_valid, fifo.r_empty]))
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