157 lines
7.4 KiB
Markdown
157 lines
7.4 KiB
Markdown
# Component Selection
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Component choices for the re-BBA-RB replacement PCB, with rationale.
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---
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## Power Architecture
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The SP1 connector supplies **12 V on pin 5**. The design needs two rails:
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| Rail | Consumers | Current budget |
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|------|-----------|----------------|
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| 3.3 V | FPGA I/O (VCCIO all banks), W5100S VCC/AVCC, config flash | ~300 mA |
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| 1.2 V | FPGA core (VCC), FPGA PLL (VCCPLL) | ~80 mA |
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A linear regulator dropping 12 V → 3.3 V at 300 mA would dissipate ~2.6 W — unacceptable in the enclosed GameCube bay. The chosen topology uses a **switching buck** for the large drop and a **low-dropout linear** for the small 3.3 V → 1.2 V step:
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```
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12 V ──► TPS562201DDCR (buck) ──► 3.3 V ──► AP2112K-1.2 (LDO) ──► 1.2 V
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~90 % efficient 105 mW dissipated
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~0.3 W heat (2.1 V × 50 mA)
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```
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Power-on sequencing is naturally correct: the LDO input is the buck output, so 1.2 V cannot rise before 3.3 V is established. The iCE40 requires core (1.2 V) ≤ I/O (3.3 V) during power-up — this topology satisfies that without any additional sequencing logic.
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---
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## Power Components
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### TPS562201DDCR — 12 V → 3.3 V Buck Converter
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| Property | Value |
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|----------|-------|
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| Manufacturer | Texas Instruments |
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| Package | SOT-23-5 (DDCR suffix) |
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| Input voltage | 4.5 – 17 V |
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| Output current | 2 A |
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| Efficiency | ~90 % at this operating point |
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| External components | Inductor + 3 capacitors |
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**Why this part:**
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The DDCR (SOT-23-5) variant was chosen over the DRLR (SOT-23-6) because the extra pin on the -6 package is only an EN (enable) control. This supply is always-on — it powers up with the GameCube and powers down with it — so EN tied to VIN internally (as the -5 package does) is the correct behaviour and removes one pin and one footprint variant to manage.
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The SOT-23-5 footprint is in KiCad's official library (`Package_TO_SOT_SMD:SOT-23-5`). The symbol is available from SnapEDA.
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**Why not a linear regulator:** dropping 8.7 V at 300 mA in a TO-252 or SOT-223 LDO dissipates ~2.6 W. A heatsink would be required and the GameCube bay has no airflow.
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---
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### AP2112K-1.2TRG1 — 3.3 V → 1.2 V LDO
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| Property | Value |
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|----------|-------|
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| Manufacturer | Diodes Inc. |
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| Package | SOT-23-5 |
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| Input voltage | 1.5 – 6 V |
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| Output voltage | 1.2 V fixed |
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| Output current | 600 mA |
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| Dropout voltage | 250 mV @ 600 mA |
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| Noise | 50 µV rms |
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**Why this part:**
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The FPGA core supply needs a fixed 1.2 V with low noise (PLL and core logic are sensitive to supply ripple). The AP2112K is widely used for exactly this purpose in iCE40 and other FPGA designs.
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Previously considered alternatives were rejected:
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- **LP2985**: no 1.2 V fixed variant in the standard product family (lowest is 2.5 V).
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- **TLV1117 fixed**: minimum fixed output is 1.25 V, not 1.2 V; the adjustable version needs two resistors and has worse accuracy.
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- **LM1117-1.2**: valid fallback, available in KiCad, but larger SOT-223 package with higher dropout.
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The AP2112K is available in the Digikey KiCad library. Heat dissipation: (3.3 − 1.2) V × 80 mA = 168 mW — well within SOT-23-5 ratings.
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---
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## Core Silicon
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### iCE40UP5K-SG48ITR — FPGA
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| Property | Value |
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|----------|-------|
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| Manufacturer | Lattice Semiconductor |
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| Package | QFN-48 (SG48), 7 × 7 mm |
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| Logic cells | 5280 LUT4 |
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| SPRAM | 128 kB (4 × SB_SPRAM256KA) |
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| I/O banks | 3 (VCCIO per bank, up to 3.3 V) |
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Unchanged from the iCEbreaker development platform. The design was written and validated for this device. The SG48 QFN package has ~34 usable I/O; the design uses 21 (5 EXI + 15 W5100 + 1 clock), leaving ~13 free for expansion or debug headers.
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Symbols and footprints: available from SnapEDA and the iCEbreaker community KiCad libraries.
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---
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### W5100S-L — Ethernet MAC/PHY
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| Property | Value |
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|----------|-------|
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| Manufacturer | WIZnet |
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| Package | QFN-48 |
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| Interface | Indirect parallel bus (IDM), A[1:0] + D[7:0] |
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| Power supply | 3.3 V single supply (internal LDO for core) |
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| Max throughput | ~27 Mbit/s (matches EXI ceiling) |
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**Why W5100S over original W5100:**
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The W5100S is a register-compatible drop-in upgrade. The firmware targets the W5100 register map, which is identical on the W5100S. Benefits of the S variant:
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- Available in QFN-48 (smaller and easier to hand-solder than LQFP)
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- Lower power consumption
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- Single 3.3 V supply — the W5100S has an internal core LDO, so no separate 1.2 V rail is needed for the ethernet chip (unlike some original W5100 versions)
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**Why parallel bus over SPI (W5500):** The parallel IDM bus runs at 24 MHz synchronous clock and achieves ~27 Mbit/s — matching the EXI ceiling. The W5500 SPI path is limited to ~12 Mbit/s by the operating logic speed on the iCE40UP5K (~40 MHz ceiling for the W5500 transaction FSM, not just the bit-bang). W5100 is the throughput path for bulk ROM streaming. See CLAUDE.md "W5100 vs W5500" for the full analysis.
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**Only 2 address pins wired (A[1:0]):** The W5100S in Indirect Data Mode (IDM) exposes only 4 registers on the bus — MR, IDM_AR0 (address high), IDM_AR1 (address low), IDM_DR (data). A[1:0] selects between them; all access to the full 16-bit register/buffer space is handled by writing the target address into IDM_AR first. The board ties A[14:2] to GND.
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WIZnet provides official KiCad symbols and footprints on their GitHub.
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---
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### W25Q32JVSSIQ — SPI Configuration Flash
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| Property | Value |
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|----------|-------|
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| Manufacturer | Winbond |
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| Package | SOIC-8 |
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| Capacity | 32 Mbit (4 MB) |
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The iCE40UP5K loads its bitstream from an external SPI flash at power-on. 32 Mbit is ample — the compressed bitstream is well under 1 MB. SOIC-8 footprint is in KiCad's official library (`Package_SO:SOIC-8`).
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---
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## Clocks
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### 12 MHz Crystal — FPGA PLL Reference
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The iCE40's internal PLL requires an external reference. The design uses 12 MHz (DIVR=0, DIVF=71, DIVQ=4) to generate 54 MHz for the EXI capture domain. The internal HFOSC (48 MHz ÷ 2 = 24 MHz) is used for the EXI and sync domains.
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Suggested footprint: 3.2 × 2.5 mm SMD crystal (e.g. ABM8G series).
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### 25 MHz Crystal — W5100S PHY Reference
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The W5100S integrated Ethernet PHY requires a 25 MHz reference crystal. Same 3.2 × 2.5 mm SMD package recommended for consistency.
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---
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## Ethernet Interface
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### Integrated MagJack (e.g. HR911105A)
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An integrated RJ45 connector with built-in magnetics and link/activity LEDs. Choosing an integrated MagJack over discrete transformer + RJ45 reduces component count, eliminates transformer placement constraints, and ensures the common-mode choke is matched to the connector.
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---
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## Ground and Power Planes
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- **Single solid GND plane** — do not split signal and power ground. At 24–27 MHz digital switching, return currents flow under their signal traces; splitting the plane forces longer return paths and increases EMI.
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- **SP1 pin 2 (shield ground)** — connect to GND plane near the connector via a 0 Ω resistor or 100 nF capacitor to allow a break point if the GameCube chassis ground introduces a ground loop during bring-up.
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- **SP1 pin 5 (12 V)** — power input to buck converter. Do not connect to any FPGA I/O.
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- **Buck converter layout** — keep the switching loop (input cap → switch node → inductor → output cap) compact and away from EXI and Ethernet signal traces.
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- **Decoupling** — 100 nF ceramic (0402) at every power pin; 100 µF bulk cap near the SP1 connector on the 3.3 V rail.
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