Roflin
d669917cfe
A captured frame proves the full EXI->FPGA->W5100->wire path works: the first 16 bytes are byte-perfect (broadcast dst, PAR0-5 source MAC, ARP ethertype). It truncates at exactly 16 = the tx_bytes FIFO depth, because TXFrameDrain waits for a length that only arrives at the ST trigger, after the whole frame has been streamed. Supersedes the previous note, which concluded it was NOT depth-related; that came from a clean-reset run whose result was invalid because the W5100 was already wedged, so nothing transmitted regardless of length. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>