d67f111019
Two coupled fixes, both exposed by batching TXDATA writes in the test app. 1. eff_addr advanced on EVERY data byte of a register-space write. But TXDATA (0x48) is a FIFO PORT, not a register: a whole frame is written to that one address. So an 8-byte write put byte 0 in TXDATA and bytes 1..7 into 0x49+, which the switch silently ignores. The frame was an eighth of its declared length, TXFrameDrain blocked waiting for the rest, and TI never set (hardware: txto=16, "no ACK after 20 tries"). SWISS WOULD HAVE HIT THIS. It writes an entire frame with bba_outs to BBA_WRTXFIFOD -- one transaction, one address -- so its TX would have delivered ONE BYTE per frame. The path was never exercised because the test app wrote TXDATA one byte per EXI transaction, giving every byte a fresh header at 0x48. Every other register must still advance, so that bba_outs can write PAR0-5 or MAR0-7 as a block; the exception is TXDATA only. 2. tx_bytes was 16 deep. SPI cannot back-pressure -- there is no way to tell the GC to wait -- so BBARegisterFile silently drops bytes when w_rdy is low, which makes the depth the only thing between a drain stall and a corrupted frame, not a buffering preference. 16 bytes is ~4.7 us at the EXI byte rate, and TXFrameDrain shares the W5100 bus arbiter with RX and the socket-3 UDP test, so any longer stall truncated a frame mid-flight. With (1) fixed, Swiss streams up to 1514 bytes in a single transaction, so 16 could never have held. Now 2048: a whole maximum-size frame plus margin, so a frame cannot be truncated even if the drain makes no progress for the entire transaction. Costs 3 of 27 free BRAMs (ICESTORM_RAM 3/30 -> 6/30, LC 68% -> 70%). Dennis spotted that the 8-byte workaround could not survive whole-frame writes, which is what prompted fixing the depth rather than shipping it. bba_tx_bytes() consequently streams 64-byte chunks (bba_write()'s buffer limit), so a 60-byte ACK is ONE transaction instead of sixty. T8 covers both and is mutation-tested: restoring the increment gives "1/8 bytes MISMATCH -- got [17], want [17, 34, 51, ...]". It now writes 64 bytes so it exercises the deepened FIFO too. --seeds 8: clk 27.6-29.4 MHz, EXI 51.2-64.7 MHz, 8/8 PASS. Best seed 1 (clk 29.35, EXI 60.80), flashed. STILL NO FLOW CONTROL on the TX path: a frame larger than 2048 would drop silently rather than error. Fine for ethernet's 1518 ceiling; revisit if the multiworld socket work ever wants larger payloads. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
159 lines
4.8 KiB
C
159 lines
4.8 KiB
C
#include "bba.h"
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#include <string.h>
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#include <unistd.h>
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#include <ogc/lwp_watchdog.h>
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u32 bba_speed = EXI_SPEED32MHZ; /* nominal name; ~27 MHz in reality */
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static int begin(void);
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static void end(void);
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u32 bba_gap_us = 16; /* see bba.h -- 0 reproduces the raw failure */
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/* Busy-wait, not usleep(): we are holding the EXI lock with CS asserted, so
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* yielding here is both unnecessary and imprecise at these timescales. */
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static void gap(void)
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{
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u64 t0;
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if (!bba_gap_us) return;
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t0 = gettime();
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while (ticks_to_microsecs(diff_ticks(t0, gettime())) < bba_gap_us) ;
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}
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/* Real GC<->BBA protocol (docs/exi_protocol_real.md), verified against libogc
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* and Swiss. Register space is a 4-byte header followed by a data phase that
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* runs until CS -- there is no length field.
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* read [0x80, addr>>8, addr&0xFF, 0x00] + N bytes
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* write [0xC0, addr>>8, addr&0xFF, 0x00] + N bytes
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* The trailing 0x00 is the device's prefetch window: the address completes a
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* whole byte before the data phase so the register file can fetch in time. */
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int begin_raw(void) { return begin(); }
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void end_raw(void) { end(); }
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static int begin(void)
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{
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int tries;
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/* EXI_Lock fails outright (rather than blocking) when another subsystem
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* holds the channel -- Swiss or a libogc driver may have it briefly.
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* Retry for ~100 ms before giving up so a transient collision does not
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* surface as a test failure. */
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for (tries = 0; tries < 100; tries++) {
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if (EXI_Lock(BBA_EXI_CHAN, BBA_EXI_DEV, NULL) > 0) break;
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usleep(1000);
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}
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if (tries == 100) return -1;
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if (EXI_Select(BBA_EXI_CHAN, BBA_EXI_DEV, bba_speed) <= 0) {
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EXI_Unlock(BBA_EXI_CHAN);
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return -2;
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}
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return 0;
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}
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static void end(void)
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{
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EXI_Deselect(BBA_EXI_CHAN);
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EXI_Unlock(BBA_EXI_CHAN);
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}
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static int put_hdr(u16 addr, int write)
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{
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u32 h = ((u32)(write ? 0xC0 : 0x80) << 24) | ((u32)addr << 8);
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if (EXI_Imm(BBA_EXI_CHAN, &h, 4, EXI_WRITE, NULL) <= 0) return -3;
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if (EXI_Sync(BBA_EXI_CHAN) <= 0) return -4;
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return 0;
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}
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int bba_read(u16 addr, void *buf, u32 len)
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{
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int rc;
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if (len < 1) return -10;
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if ((rc = begin()) < 0) return rc;
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if ((rc = put_hdr(addr, 0)) < 0) { end(); return rc; }
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gap();
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memset(buf, 0, len);
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if (EXI_ImmEx(BBA_EXI_CHAN, buf, len, EXI_READ) <= 0) { end(); return -5; }
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end();
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return 0;
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}
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int bba_write(u16 addr, const void *buf, u32 len)
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{
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int rc;
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u8 tmp[64];
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if (len < 1 || len > sizeof(tmp)) return -10;
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memcpy(tmp, buf, len);
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if ((rc = begin()) < 0) return rc;
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if ((rc = put_hdr(addr, 1)) < 0) { end(); return rc; }
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if (EXI_ImmEx(BBA_EXI_CHAN, tmp, len, EXI_WRITE) <= 0) { end(); return -6; }
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end();
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return 0;
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}
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int bba_devid(u8 id[4])
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{
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int rc;
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u16 h = 0x0000; /* command space, reg 0, read */
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if ((rc = begin()) < 0) return rc;
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if (EXI_Imm(BBA_EXI_CHAN, &h, 2, EXI_WRITE, NULL) <= 0) { end(); return -3; }
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if (EXI_Sync(BBA_EXI_CHAN) <= 0) { end(); return -4; }
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gap();
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memset(id, 0, 4);
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if (EXI_ImmEx(BBA_EXI_CHAN, id, 4, EXI_READ) <= 0) { end(); return -5; }
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end();
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return 0;
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}
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int bba_r8(u16 addr)
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{
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u8 v;
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int rc = bba_read(addr, &v, 1);
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return rc < 0 ? rc : (int)v;
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}
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int bba_w8(u16 addr, u8 val)
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{
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return bba_write(addr, &val, 1);
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}
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int bba_stream(u16 addr, void *buf, u32 len)
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{
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/* Identical to bba_read now: the real protocol always streams until CS,
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* so there is no separate "DMA" header form. */
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return bba_read(addr, buf, len);
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}
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int bba_tx_bytes(const u8 *buf, u32 len)
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{
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u32 off = 0;
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/* Stream in 64-byte chunks, ONE EXI transaction each.
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*
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* Writing byte by byte with bba_w8() costs a full EXI_Lock / EXI_Select /
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* header / EXI_Deselect / EXI_Unlock PER BYTE -- about sixty transactions
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* for one 60-byte ACK. That latency is why ~1/3 of netboot blocks were
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* retried: the ACK always reached the W5100 (txto=0, TI always set) but
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* missed the host's timeout.
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*
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* ⚠️ BUT THE CHUNK SIZE IS BOUNDED BY tx_bytes, WHICH IS 16 DEEP.
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* BBARegisterFile silently drops bytes when tx_bytes.w_rdy is low,
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* because SPI cannot back-pressure. Within one transaction the bytes
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* arrive back-to-back at EXI speed -- far faster than TXFrameDrain can
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* start consuming -- so a 64-byte chunk overran the FIFO, the frame went
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* out truncated, and the host saw no valid ACK at all ("no ACK after 20
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* tries"). Byte-by-byte worked only because the per-byte EXI overhead
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* happened to give the drain time.
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*
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* tx_bytes is now 2048 deep -- a whole maximum-size frame -- so the old
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* 8-byte cap is gone and 64 (bba_write()'s buffer limit) sends a 60-byte
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* ACK in a SINGLE transaction. The depth is what makes this safe: SPI
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* cannot back-pressure, so the FIFO must absorb the entire burst. */
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while (off < len) {
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u32 n = len - off;
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int rc;
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if (n > 64) n = 64;
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rc = bba_write(REG_TXDATA, buf + off, n);
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if (rc < 0) return rc;
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off += n;
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}
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return 0;
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}
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