Roflin
d95f2147a4
Hardware speed sweep after the Mode 3 fix: ok=[1,1,1,0,0,0] -- register reads are CORRECT up to 4 MHz and fail from 8 MHz. The MOSI edge fix works and the gateware is functionally correct; what remains is a fixed MISO output delay of ~3 capture ticks (~55 ns: 2 stages of input FFSynchronizer plus 1 tick to register the shift). At 27 MHz that is ~2 bits, which is exactly the observed NWAYS read of 05 C0 = 0x17 >> 2, and the 250ns-pass / 125ns-fail threshold brackets the delay at 60-125 ns. Also records that lowering the EXI clock is not available: Swiss hardcodes EXI_SPEED_32MHZ in exi_select(). Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>