Roflin
399fbf02a4
tx_fifo.r_en popped from txld_cnt >= 2, hard-coded for the old invented 2-byte header where the data phase began at slot 2. The real protocol's register space uses a 4-byte header, so data starts at slot 4 -- two bytes were being consumed before the GC clocked any data, and every register read came back wrong. On hardware: HIPR and NWAYS both read 0x00, and the device ID returned 01 80 c0 c0 (stale bytes, including our own header command bytes 0x80/0xC0 echoing back out of the FIFO). The threshold is now derived from byte 0 bit 7, which is exactly what selects the header form: register space -> 4 slots, command space -> 2 slots. Also removes the pad-slot filler byte the register file was pushing. That was compensating for this bug rather than fixing it -- it made the simulation pass while hardware still failed, which is how it slipped through. With the pop threshold correct the filler is wrong, and both the unit and integration testbenches agree without it. All suites pass: bba_register_file, bba_top, exi_capture, exi_j4, spi_mode3_slave, tx_frame_drain, spram_arbiter, rx_frame_assembler, w5100_parallel_master. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
298 lines
13 KiB
Python
298 lines
13 KiB
Python
"""ExiCapture — fast EXI byte-capture front-end (capture domain, 54 MHz).
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Wraps the SPIMode3Slave bit engine and bridges it to the slower `exi` domain
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(24 MHz) through two AsyncFIFOs:
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capture (54 MHz) exi (24 MHz)
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┌────────────────────┐ rx_fifo ───► received bytes (header + data)
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│ SPIMode3Slave │ (8-bit, capture→exi)
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│ (bit engine) │ tx_fifo ◄─── response bytes to drive on MISO
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└────────────────────┘ (8-bit, exi→capture)
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Why split: the bit engine must oversample a 27 MHz EXI clock 2×, which needs a
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54 MHz clock — far faster than the register-file logic can close (~44 MHz).
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Only this small, shallow front-end runs fast; everything else stays at 24 MHz.
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TX response gating
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------------------
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Every EXI transaction begins with 2 header bytes (write_flag/addr/len) during
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which the GC ignores MISO. The core cannot have produced a response yet (it
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hasn't even decoded the header), so the wrapper must NOT pop tx_fifo for those
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2 bytes. A per-transaction counter (`txld_cnt`, reset by frame_start) gates the
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pop: header bytes drive a don't-care 0xFF; from the first data byte onward the
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wrapper pops tx_fifo (one byte per tx_load). `tx_hold` is registered at tx_load
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time — before the FIFO advances — so the bit engine latches the correct byte on
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the following SPI rising edge (the classic FWFT-advance off-by-one is avoided).
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"""
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from amaranth import *
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from amaranth.lib.cdc import FFSynchronizer
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from amaranth.lib.fifo import AsyncFIFO
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from exi_bba.spi_mode3_slave import SPIMode3Slave
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__all__ = ["ExiCapture"]
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class ExiCapture(Elaboratable):
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"""EXI front-end: SPI bit engine (capture domain) + byte FIFOs to core.
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Physical SPI pins (capture domain)
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----------------------------------
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spi_clk / spi_mosi / spi_cs_n : raw async inputs from the GC
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spi_miso : output to the GC
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Core-facing RX byte stream (core domain, FWFT read side of rx_fifo)
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------------------------------------------------------------------
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rx_data : current received byte
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rx_rdy : a received byte is available
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rx_en : pop (assert for one core cycle to consume rx_data)
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Core-facing TX byte stream (core domain, write side of tx_fifo)
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--------------------------------------------------------------
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tx_data : response byte to enqueue
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tx_en : write strobe
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tx_rdy : tx_fifo has room
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"""
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def __init__(self, rx_depth=4, tx_depth=2):
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self._rx_depth = rx_depth
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self._tx_depth = tx_depth
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# Physical SPI (capture domain, wired to pins by BBATop)
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self.spi_clk = Signal(init=1)
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self.spi_mosi = Signal()
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self.spi_cs_n = Signal(init=1)
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self.spi_miso = Signal()
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# Core-facing RX read side
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self.rx_data = Signal(8)
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self.rx_rdy = Signal()
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self.rx_en = Signal()
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# Core-facing TX write side
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self.tx_data = Signal(8)
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self.tx_en = Signal()
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self.tx_rdy = Signal()
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# Core-facing: high (exi domain) while a transaction is in progress.
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# The register file uses it to stream variable-length (DMA) reads until
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# CS deasserts.
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self.cs_active = Signal()
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def elaborate(self, platform):
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m = Module()
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spi = SPIMode3Slave(domain="capture")
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m.submodules.spi = spi
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rx_fifo = AsyncFIFO(width=8, depth=self._rx_depth,
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w_domain="capture", r_domain="exi")
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tx_fifo = AsyncFIFO(width=8, depth=self._tx_depth,
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w_domain="exi", r_domain="capture")
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m.submodules.rx_fifo = rx_fifo
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m.submodules.tx_fifo = tx_fifo
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# cs_active (capture) → exi domain for the register file
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m.submodules.cs_sync = FFSynchronizer(spi.cs_active, self.cs_active,
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o_domain="exi")
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# ── Physical pins ↔ bit engine ───────────────────────────────────
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m.d.comb += [
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spi.spi_clk .eq(self.spi_clk),
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spi.spi_mosi.eq(self.spi_mosi),
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spi.spi_cs_n.eq(self.spi_cs_n),
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self.spi_miso.eq(spi.spi_miso),
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]
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# ── RX: every received byte → rx_fifo (capture write side) ───────
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m.d.comb += [
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rx_fifo.w_data.eq(spi.rx_byte),
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rx_fifo.w_en .eq(spi.rx_valid),
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]
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# Core read side
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m.d.comb += [
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self.rx_data .eq(rx_fifo.r_data),
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self.rx_rdy .eq(rx_fifo.r_rdy),
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rx_fifo.r_en .eq(self.rx_en),
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]
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# ── TX: core write side ──────────────────────────────────────────
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m.d.comb += [
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tx_fifo.w_data.eq(self.tx_data),
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tx_fifo.w_en .eq(self.tx_en),
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self.tx_rdy .eq(tx_fifo.w_rdy),
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]
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# ── TX response gating (capture domain) ──────────────────────────
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# The bit engine drives MISO LIVE from tx_byte = tx_fifo head, so the
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# response byte at the head is what gets sent for the current data byte.
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# `txld_cnt` counts completed bytes within the transaction (tx_load
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# pulses at each byte completion):
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# completion 0,1 → header bytes (no pop)
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# completion ≥2 → a data byte finished → pop to advance the head
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# The first data byte (data0) is served live from the head without a
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# pop; the pop after it advances the head to data1's response, etc.
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txld_cnt = Signal(3) # counts header slots; data starts at hdr_slots
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m.d.comb += spi.tx_byte.eq(tx_fifo.r_data)
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# Pop depends ONLY on the registered tx_load and txld_cnt — NOT on
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# frame_start. (frame_start precedes byte-0's tx_load by a cycle and
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# has already reset txld_cnt to 0, so byte 0 is never a data byte.)
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# Keeping cs_fall/frame_start off the pop path shortens the capture-
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# domain critical path through the FIFO consume pointer.
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#
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# `flushing` clears prefetch over-push left in tx_fifo by the previous
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# transaction: the register file streams response bytes ahead of the GC
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# clock for DMA reads, so when CS deasserts mid-stream a few unsent
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# bytes remain. On CS-fall (frame_start) drain tx_fifo to empty before
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# the new transaction's data phase, so stale bytes never reach MISO.
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# The flush must NOT read `tx_fifo.r_rdy`. r_rdy is derived from the
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# gray-coded FIFO pointers that `r_en` advances, so any r_rdy → r_en
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# dependence (either gating the drain with `& r_rdy`, or deasserting a
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# `flushing` flag on `~r_rdy`) closes a long capture-domain loop
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# (consume_ptr → gray → r_rdy → flush → r_en → consume_ptr) — the
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# measured critical path capping capture_clk. Instead, drain for a
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# FIXED number of cycles: the FIFO is only `tx_depth` deep, so pulsing
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# r_en for `tx_depth + 1` cycles empties it regardless of occupancy
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# (the FIFO advances its read pointer only on r_en & r_rdy internally,
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# so pulses past empty are harmless). This removes the pointer
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# feedback from r_en entirely; the only remaining r_en source is the
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# legitimate data-byte pop.
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drain = Signal(range(self._tx_depth + 2))
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with m.If(spi.frame_start):
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m.d.capture += drain.eq(self._tx_depth + 1)
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with m.Elif(drain != 0):
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m.d.capture += drain.eq(drain - 1)
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# Pops must start at the FIRST DATA SLOT, which depends on the header
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# length -- and the real protocol has two header forms (see
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# docs/exi_protocol_real.md):
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# byte0 bit7 = 1 register space, 4-byte header -> data at slot 4
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# byte0 bit7 = 0 command space, 2-byte header -> data at slot 2
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# This was hard-coded to 2, which is right only for the old invented
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# 2-byte header; against a 4-byte header it consumes two bytes before
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# the GC clocks any data and every read comes back shifted.
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hdr_slots = Signal(3, init=2)
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first_byte = Signal(init=1)
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with m.If(spi.frame_start):
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m.d.capture += first_byte.eq(1)
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with m.Elif(spi.rx_valid & first_byte):
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m.d.capture += [first_byte.eq(0),
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hdr_slots.eq(Mux(spi.rx_byte[7], 4, 2))]
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m.d.comb += tx_fifo.r_en.eq(
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(spi.tx_load & (txld_cnt >= hdr_slots)) | (drain != 0)
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)
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with m.If(spi.frame_start):
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m.d.capture += txld_cnt.eq(0)
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with m.Elif(spi.tx_load & (txld_cnt < 5)):
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m.d.capture += txld_cnt.eq(txld_cnt + 1)
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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dut = ExiCapture()
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errors = []
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# SPI half-period in capture ticks. At 54 MHz capture / 27 MHz EXI the real
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# ratio is ~2; use 4 here for a clean, well-oversampled functional check.
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HALF = 4
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async def spi_byte(ctx, mosi_val):
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"""Clock one SPI Mode 3 byte; return the assembled MISO byte."""
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miso = 0
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for bit in range(7, -1, -1):
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ctx.set(dut.spi_mosi, (mosi_val >> bit) & 1)
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ctx.set(dut.spi_clk, 0)
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await ctx.tick("capture").repeat(HALF)
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miso = (miso << 1) | ctx.get(dut.spi_miso)
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ctx.set(dut.spi_clk, 1)
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await ctx.tick("capture").repeat(HALF)
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return miso
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async def core_drain_rx(ctx, into):
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"""Pop one byte from the core RX side if available."""
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if ctx.get(dut.rx_rdy):
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into.append(ctx.get(dut.rx_data))
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ctx.set(dut.rx_en, 1)
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await ctx.tick("exi").repeat(1)
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ctx.set(dut.rx_en, 0)
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return True
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return False
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async def push_tx(ctx, b):
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ctx.set(dut.tx_data, b)
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ctx.set(dut.tx_en, 1)
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await ctx.tick("exi").repeat(1)
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ctx.set(dut.tx_en, 0)
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async def do_txn(ctx, hdr, responses, n_data, rx_seen):
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"""One EXI transaction: clock `hdr` bytes, model the clock-idle gap
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(drain rx + prefetch `responses` into tx_fifo), then clock `n_data`
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data bytes; return the MISO data bytes read."""
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ctx.set(dut.spi_cs_n, 0)
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ctx.set(dut.spi_clk, 1)
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await ctx.tick("capture").repeat(HALF)
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for h in hdr:
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await spi_byte(ctx, h)
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for _ in range(20): # clock-idle gap
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await core_drain_rx(ctx, rx_seen)
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await ctx.tick("exi").repeat(1)
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for r in responses:
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await push_tx(ctx, r)
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await ctx.tick("capture").repeat(2)
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miso = [await spi_byte(ctx, 0x00) for _ in range(n_data)]
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ctx.set(dut.spi_cs_n, 1)
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await ctx.tick("capture").repeat(HALF)
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for _ in range(20): # drain data-phase dummies
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await core_drain_rx(ctx, rx_seen)
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await ctx.tick("exi").repeat(1)
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return miso
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async def testbench(ctx):
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rx_seen = []
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await ctx.tick("capture").repeat(2)
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# ── T1: header + 2 data bytes read back ──────────────────────────
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miso = await do_txn(ctx, [0x12, 0x34], [0xA5, 0x5A], 2, rx_seen)
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print(f"T1 rx={[hex(b) for b in rx_seen[:2]]} MISO={[f'0x{b:02X}' for b in miso]}")
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if rx_seen[:2] != [0x12, 0x34]:
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errors.append(f"T1 header rx wrong: {rx_seen[:2]}")
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if miso != [0xA5, 0x5A]:
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errors.append(f"T1 MISO wrong: {[hex(b) for b in miso]}")
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# ── T2: prefetch over-push must NOT leak into the next transaction ─
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# Txn A pushes 2 responses but the GC clocks only 1 data byte, leaving
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# one stale byte in tx_fifo. Txn B must read its OWN fresh responses,
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# proving the CS-fall flush cleared the stale prefetch.
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rx_seen.clear()
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await do_txn(ctx, [0x12, 0x34], [0xA5, 0x5A], 1, rx_seen) # leaves 0x5A
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misoB = await do_txn(ctx, [0x12, 0x34], [0x11, 0x22], 2, rx_seen)
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print(f"T2 MISO after over-push: {[f'0x{b:02X}' for b in misoB]} (want 0x11 0x22)")
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if misoB != [0x11, 0x22]:
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errors.append(f"T2 flush failed — stale byte leaked: {[hex(b) for b in misoB]}")
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sim = Simulator(dut)
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sim.add_clock(Period(MHz=54), domain="capture")
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sim.add_clock(Period(MHz=24), domain="exi")
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sim.add_testbench(testbench)
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with sim.write_vcd("ExiCapture.vcd"):
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sim.run()
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if errors:
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print("\nFAILURES:")
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for e in errors:
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print(" ", e)
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sys.exit(1)
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else:
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print("\nAll tests passed.")
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