Roflin
a3b3e052bc
Replaces 54 MHz oversampling with a slave clocked by EXI CLK itself:
exiclk posedge sample MOSI (Mode 3 samples on edge 2)
exiclk_n negedge drive MISO (must settle between the master's samples)
CS_N async reset for both
EXI CLK (pin 44) is at die (6,0) = global buffer net 6 on the 5k-sg48, so it
can drive a real clock network with no board change.
This removes the capture domain entirely. Bit-level timing no longer
crosses a clock boundary -- MISO is clock-to-Q instead of 3 ticks of a foreign
clock -- and the only crossings left are the byte FIFOs, which have a whole
byte-time (~296 ns) of slack rather than a fraction of a bit.
AsyncFIFO needs a posedge clock for its internal reset CDC, so the FIFO sides
use reset-less POSEDGE domains on the same pin; the engine pops on the posedge
and hands the byte to the negedge output stage through a register. The FIFOs
must not see CS: resetting one side of an AsyncFIFO desynchronises its gray
pointers.
Two bugs found and fixed along the way:
* one pop per byte boundary is all that is needed -- pops during the header
drain whatever the previous transaction left (replacing the CS-fall flush)
and the turnaround-byte push lands in data slot 0. No slot-threshold or
header-length logic at all.
* rx_byte/rx_valid had to become COMBINATIONAL. Registered, they need one
more clock edge, and after a transaction's final bit the clock stops and
CS rises -- so the last byte of every transaction was lost (a 4-byte write
landed as DE AD BE 00, a 34-byte TX as 15 bytes).
At the HARDWARE rate (EXI_HALF=1, 27 MHz) the device ID, NWAYS, PAR
read/write and the W5100->SPRAM RX path now all pass -- none of which has ever
worked at 27 MHz before. Testbenches now drive the SPI clock with real
delays, since there is no capture domain to count ticks against.
STILL BROKEN: the SPRAM/DMA stream is offset by one byte (its round trip
exceeds the single turnaround byte), and TX lands 15 of 34 bytes. Do not
flash this yet.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
141 lines
6.4 KiB
Python
141 lines
6.4 KiB
Python
"""SPI Mode 3 byte-oriented slave for the EXI bus — CLOCKED BY EXI CLK.
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CPOL=1, CPHA=1 (real Mode 3): CLK idles HIGH, the master CHANGES MOSI on the
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falling edge and both ends SAMPLE on the rising edge.
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Architecture
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------------
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The engine is clocked by the EXI clock itself rather than oversampling it from
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a faster domain:
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exiclk posedge of EXI CLK — sample MOSI, assemble RX bytes
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exiclk_n negedge of EXI CLK — drive MISO (must change BETWEEN the
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master's sampling edges)
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CS_N asynchronous reset for both
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Why, and what it fixes (hardware 2026-10-03)
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--------------------------------------------
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The previous version oversampled EXI CLK from a 54 MHz `capture` domain, which
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put BIT-level timing across a clock-domain boundary: the engine's view of the
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clock lagged the pin by 2 stages of `FFSynchronizer` plus a register, ~3 ticks
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≈ 55 ns. One EXI bit at 27 MHz is 37 ns, so MISO came out ~2 bits late and the
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master read `0x17` as `05 C0` (= `0x17 >> 2`). Register reads were correct up
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to 4 MHz and failed from 8 MHz — the sweep read `ok=[1,1,1,0,0,0]`.
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No amount of oversampling fixes that: at 54 MHz there are only 2 ticks per bit,
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and the design cannot close the 81 MHz that 3x would need. Clocking the engine
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from the EXI pin makes MISO clock-to-Q instead, and moves the ONLY remaining
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crossing to the byte-level AsyncFIFOs, which have a whole byte-time (~296 ns at
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27 MHz) of slack instead of a fraction of a bit.
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EXI CLK (pin 44) sits at die (6,0) on the 5k-sg48, which is global buffer input
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net 6 — so it can drive a real clock network with no board change.
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The domains are created by the PARENT (`ExiCapture`) so the byte FIFOs can name
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them; this module just uses `m.d.exiclk` / `m.d.exiclk_n`.
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"""
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from amaranth import *
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__all__ = ["SPIMode3Slave"]
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class SPIMode3Slave(Elaboratable):
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"""Byte-oriented SPI Mode 3 slave, clocked by the EXI clock.
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Ports
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-----
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spi_clk / spi_mosi / spi_cs_n : raw inputs from the GC. spi_clk drives the
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exiclk/exiclk_n domains and spi_cs_n their async reset (both wired by
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the parent); they are still listed here so the module is self-describing
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and so spi_cs_n can gate MISO combinationally.
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spi_miso : output to the GC; idles HIGH while CS is deasserted.
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rx_byte : last complete received byte (valid while rx_valid is high)
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rx_valid : 1-cycle pulse in `exiclk` when rx_byte holds a new byte
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tx_byte : byte to transmit; sampled at each byte boundary
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tx_load : 1-cycle pulse in `exiclk_n` asking upstream for the next byte
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hdr_bytes : how many leading bytes are header (MISO don't-care). Pops are
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suppressed until past them, so the first response byte the register
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file pushes lands in data slot 0 rather than being eaten by the header.
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"""
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def __init__(self):
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self.spi_clk = Signal(init=1) # idles HIGH
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self.spi_mosi = Signal()
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self.spi_cs_n = Signal(init=1) # active LOW
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self.spi_miso = Signal(init=1)
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self.rx_byte = Signal(8)
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self.rx_valid = Signal()
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self.tx_byte = Signal(8)
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self.tx_load = Signal()
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# Header length for this transaction, in bytes. The real protocol has
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# two forms selected by bit 7 of byte 0 (see docs/exi_protocol_real.md):
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# register space = 4-byte header, command space = 2-byte.
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self.hdr_bytes = Signal(3, init=4)
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# Transaction framing, generated in the slow domain by the parent.
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self.frame_start = Signal()
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self.cs_active = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── RX: sample MOSI on the RISING edge (Mode 3 samples on edge 2) ──
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rx_shift = Signal(8)
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rx_bit = Signal(3)
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byte_idx = Signal(3, init=0) # bytes seen this transaction (saturating)
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nxt = Cat(self.spi_mosi, rx_shift[:-1]) # MSB-first: shift left, new bit at LSB
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m.d.exiclk += rx_shift.eq(nxt)
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m.d.exiclk += rx_bit.eq(rx_bit + 1)
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with m.If(rx_bit == 7):
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with m.If(byte_idx != 7):
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m.d.exiclk += byte_idx.eq(byte_idx + 1)
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# rx_byte/rx_valid are COMBINATIONAL, not registered. The clock stops
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# and CS rises immediately after a transaction's final bit, so a
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# registered pulse would need one more clock edge that never arrives
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# and the LAST byte of every transaction would be silently lost
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# (symptom: a 4-byte write landed as DE AD BE 00, and a 34-byte TX
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# stream as 15 bytes). Driving them combinationally makes the FIFO
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# capture the byte on the very edge that completes it.
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m.d.comb += self.rx_byte .eq(nxt)
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m.d.comb += self.rx_valid.eq(rx_bit == 7)
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# ── TX: pop on the POSEDGE, present on the NEGEDGE ────────────────
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# AsyncFIFO needs a posedge clock internally, so the FIFO is read in
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# `exiclk` and the byte is handed to the negedge side through a plain
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# register. posedge -> negedge of the SAME clock is a half-period
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# path (18.5 ns at 27 MHz), which is ample.
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#
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# One pop per byte boundary, unconditionally. The byte popped at the
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# end of byte N is presented during byte N+1, so:
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# - pops during the header drain whatever the previous transaction
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# left in the FIFO (this replaces the old CS-fall flush), and
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# - the response the register file pushes during the protocol's
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# turnaround byte is popped at that byte's end and lands in data
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# slot 0, exactly where it belongs.
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# No header-length or slot-threshold logic is needed at all.
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tx_hold = Signal(8)
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m.d.comb += self.tx_load.eq(rx_bit == 7)
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with m.If(rx_bit == 7):
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m.d.exiclk += tx_hold.eq(self.tx_byte)
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# MISO must settle on the falling edge, before the master samples it
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# on the rising one. Driving it on the rising edge is one bit late by
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# construction -- that was the 05 C0 bug.
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tx_shift = Signal(8)
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tx_bit = Signal(3)
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m.d.exiclk_n += tx_bit.eq(tx_bit + 1)
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with m.If(tx_bit == 0):
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m.d.exiclk_n += tx_shift.eq(tx_hold) # first falling edge: MSB
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with m.Else():
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m.d.exiclk_n += tx_shift.eq(Cat(0, tx_shift[:-1]))
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m.d.comb += self.spi_miso.eq(Mux(self.spi_cs_n, 1, tx_shift[7]))
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return m
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