Roflin
2458884160
Replaces the invented 2-byte header (addr split across both bytes, 2-bit
length field) with the protocol libogc and Swiss actually speak:
command (bit7=0, 6-bit reg) [reg, 00, 00, data] one 4-byte transfer
register (bit7=1, 16-bit reg) [0x80|w<<6, ah, al, 00] + data until CS
This was not an optimisation: the old decoder read Swiss's NWAYS read
(80 00 31 00) as 'write 0x31 to NCRA', and bit 0 of 0x31 is RESET, so every
register read would have reset the device.
Changes:
* 16-bit address; no length field -- register reads and writes now stream
until CS, like the SPRAM path already did
* RHDR_LO starts the SPRAM fetch as soon as the address completes, using
the trailing header byte as the prefetch window the protocol provides
* command space serves EXI regs 0x02/0x03 (interrupt mask/status), the only
two Swiss uses
* EXI_GetID gets its own path: it offers just ONE header byte of warning, so
the first ID byte is pushed the instant byte 0 identifies the query
Two timing subtleties, both found by simulation and commented in place:
* MISO is driven LIVE from the tx FIFO head, so a byte pushed while the pad
byte is on the wire appears in the pad slot. A filler byte is parked
there (MISO is don't-care through the header) so the first real response
lands in data slot 0.
* the prefetch must be one-shot; re-firing while waiting for the pad byte
consumed the register stream early and shifted reads by a byte.
All testbenches updated to the real format and passing: bba_register_file
(7), bba_top (8 incl. the full W5100->SPRAM->GC loop and TX), exi_j4,
exi_capture, spi_mode3_slave, tx_frame_drain, spram_arbiter,
rx_frame_assembler, w5100_parallel_master. gc_bba_test rebuilt against the
new protocol.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
89 lines
3.2 KiB
C
89 lines
3.2 KiB
C
/* bba.h — raw EXI transport to the re-bba-rb adapter in Serial Port 1.
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*
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* Deliberately NOT libogc's bba network driver: this talks to the register
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* file directly so every check gets its own pass/fail and a failure points at
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* a specific register rather than at "networking".
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*/
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#ifndef BBA_H
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#define BBA_H
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#include <gccore.h>
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/* Serial Port 1 == EXI channel 0, device 2. */
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#define BBA_EXI_CHAN EXI_CHANNEL_0
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#define BBA_EXI_DEV EXI_DEVICE_2
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/* Register map (see CLAUDE.md "Key Registers"). */
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#define REG_NCRA 0x00
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#define REG_IMR 0x08
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#define REG_IR 0x09
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#define REG_RWP_LO 0x16
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#define REG_RWP_HI 0x17
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#define REG_RRP_LO 0x18
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#define REG_PAR0 0x20
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#define REG_PAR4 0x24
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#define REG_NWAYS 0x31
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#define REG_TWD_LO 0x34
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#define REG_TWD_HI 0x35
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#define REG_HIPR 0x3A
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#define REG_TXDATA 0x48
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#define SPRAM_BASE 0x0100
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/* NCRA bits */
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#define NCRA_RESET 0x01
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#define NCRA_ST0 0x02
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#define NCRA_SR 0x08
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/* IR bits */
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#define IR_RI 0x02
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#define IR_TI 0x04
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/* Expected constants */
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#define NWAYS_LINKUP 0x17
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#define HIPR_PRESENT 0x01
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/* EXI clock index, EXI_SPEED1MHZ(0) .. EXI_SPEED32MHZ(5). The nominal 32 MHz
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* index is really ~27 MHz on hardware (see CLAUDE.md); the capture domain
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* oversamples it 2x at 54 MHz. Settable so the suite can sweep it. */
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extern u32 bba_speed;
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/* Microseconds to hold the clock idle between the header write and the data
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* phase, with CS still asserted. The register file decodes the header and
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* PROACTIVELY pushes the response into its TX FIFO during this gap; until the
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* first byte reaches the FIFO head the device drives MISO low. Measured on
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* hardware 2026-10-03: at EXI index 5 the reply arrived 22 bit-times (~815 ns)
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* late with no explicit gap, so a 4-byte read returned 00 00 00 10 -- the
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* correct stream, just shifted out of the window. 0 = whatever gap libogc's
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* inter-call overhead happens to give. */
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extern u32 bba_gap_us;
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/* All return 0 on success, negative on an EXI-layer failure. */
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/* REGISTER-space read: 4-byte header [0x80, ah, al, 0x00] then `len` bytes.
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* The real protocol has NO length field -- the data phase runs until CS, so
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* `len` is unbounded. The trailing 0x00 header byte is the device's prefetch
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* window. See docs/exi_protocol_real.md. */
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int bba_read(u16 addr, void *buf, u32 len);
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/* REGISTER-space write: 4-byte header [0xC0, ah, al, 0x00] then `len` bytes. */
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int bba_write(u16 addr, const void *buf, u32 len);
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/* EXI_GetID: write 0x0000 (two bytes) then read 4. Returns the device ID,
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* which is a ONE-SHOT -- the first NCRA reset clears it until power cycle. */
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int bba_devid(u8 id[4]);
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/* Convenience single-byte helpers. bba_r8 returns the byte, or <0 on error. */
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int bba_r8(u16 addr);
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int bba_w8(u16 addr, u8 val);
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/* SPRAM / DMA-style read: any address >= 0x0100 streams until CS deasserts,
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* so `len` may exceed 4 and the header's 2-bit length field is ignored. */
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int bba_stream(u16 addr, void *buf, u32 len);
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/* Stream `len` bytes into the TXDATA port. One byte per EXI transaction:
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* the register file's effective address auto-increments per data byte, so a
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* multi-byte write to 0x48 would spill into 0x49+ instead of the FIFO. */
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int bba_tx_bytes(const u8 *buf, u32 len);
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#endif
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