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Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module.
2021-02-15 22:40:12 +01:00
build/.Xil
build/xsim.dir
Initial work on decoder Decode the LD SP, $nnnn instruction as our first three-byte instruction.
2021-02-16 22:13:50 +01:00
build/*.wcfg
Implement ld r, r
2021-02-22 22:42:40 +01:00
build/vivado_*
Complete rewrite from scratch, bootstrap WIP Rewrite to use several bus multiplexers, resulting into a less messy microarchitecture (hopefully). Some more room for cleanup though... Supports every instruction from the bootstrap rom, more or less. LY hacked at 0x90 to progress through vsync instantly. No cartridge is present yet, so we will always fail checksum test and lock up.
2023-10-02 00:00:56 +02:00
build/vivado.*
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