348 lines
18 KiB
Systemverilog
348 lines
18 KiB
Systemverilog
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`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module idec (
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input logic [7:0] instr_i[2:0],
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input logic is_ex1_i,
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input logic is_ex2_i,
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input logic is_ex3_i,
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output logic req_instr1_o,
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output logic req_instr2_o,
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output logic req_ex2_o,
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output logic req_ex3_o,
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output bus_ctrl_t bus_x_ctrl_o,
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output bus_ctrl_t bus_y_ctrl_o,
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output bus16_ctrl_t bus_p_ctrl_o,
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output bus16_ctrl_t bus_q_ctrl_o,
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output reg8_t reg8_src_o,
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output reg8_t reg8_dest_o,
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output reg16_t reg16_sel_o,
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output alu_ctrl_t alu_ctrl_o,
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output logic alu16_inc_o,
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output logic alu16_dec_o,
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output addr_src_t addr_src_o,
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output logic pc_we_o,
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output logic pc_we_cc_o,
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output cc_t cc_o,
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output pc_src_t pc_src_o,
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output logic instr_undef_o
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);
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logic [1:0] dec_x;
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logic [2:0] dec_y;
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logic [2:0] dec_z;
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logic [1:0] dec_p;
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logic dec_q;
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logic is_alu_a_r;
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logic is_alu_a_n;
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logic is_ld_sp_nnnn;
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logic is_ld_rr_nnnn;
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logic is_ld_pnnnn_a;
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logic is_ldd_hl_a;
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logic is_ldi_hl_a;
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logic is_ldd_a_hl;
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logic is_ldi_a_hl;
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logic is_cb;
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logic is_ld_r_r;
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logic is_ld_r_n;
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logic is_ldh_c_a;
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logic is_ldh_n_a;
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logic is_ldh_a_n;
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logic is_ld_rr_a;
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logic is_ld_a_pbc;
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logic is_ld_a_pde;
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logic is_ld_a_nn;
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logic is_bit_n_r;
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logic is_shift_r;
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logic is_rla;
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logic is_inc_r;
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logic is_dec_r;
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logic is_jr_cc_nn;
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logic is_jr_nn;
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logic is_call_nn;
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logic is_ret;
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logic is_push_rr;
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logic is_pop_rr;
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logic is_inc_rr;
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logic is_dec_rr;
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reg8_t reg8_src;
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reg8_t reg8_dest;
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reg16_t reg16_sel;
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assign req_instr1_o = is_ld_sp_nnnn | is_ld_rr_nnnn | is_call_nn | is_ld_pnnnn_a | is_cb | is_jr_nn | is_jr_cc_nn | is_ld_r_n | is_ldh_n_a | is_ldh_a_n | is_alu_a_n;
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assign req_instr2_o = is_ld_sp_nnnn | is_ld_rr_nnnn | is_call_nn | is_ld_pnnnn_a;
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assign req_ex2_o = is_call_nn | is_ret | is_push_rr | is_pop_rr | ((is_ld_r_r | is_alu_a_r) & (reg8_src == REG8_PHL));
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assign req_ex3_o = is_ret | is_pop_rr;
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assign dec_x = instr_i[0][7:6];
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assign dec_y = instr_i[0][5:3];
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assign dec_z = instr_i[0][2:0];
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assign dec_p = instr_i[0][5:4];
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assign dec_q = instr_i[0][3];
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assign is_jr_nn = instr_i[0] == 8'h18;
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assign is_cb = instr_i[0] == 8'hCB;
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assign is_call_nn = instr_i[0] == 8'hCD;
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assign is_ret = instr_i[0] == 8'hC9;
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assign is_ldh_c_a = instr_i[0] == 8'hE2;
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assign is_ldh_n_a = instr_i[0] == 8'hE0;
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assign is_ldh_a_n = instr_i[0] == 8'hF0;
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assign is_ld_pnnnn_a = instr_i[0] == 8'hEA;
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assign is_jr_cc_nn = (dec_x == 2'h0) & (dec_z == 2'h0) & dec_y[2];
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assign is_ld_rr_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
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assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
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assign is_ldi_hl_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h2);
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assign is_ldd_hl_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h3);
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assign is_ld_a_pbc = (dec_x == 2'h0) & (dec_z == 3'h2) & dec_q & (dec_p == 2'h0);
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assign is_ld_a_pde = (dec_x == 2'h0) & (dec_z == 3'h2) & dec_q & (dec_p == 2'h1);
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assign is_ldi_a_hl = (dec_x == 2'h0) & (dec_z == 3'h2) & dec_q & (dec_p == 2'h2);
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assign is_ldd_a_hl = (dec_x == 2'h0) & (dec_z == 3'h2) & dec_q & (dec_p == 2'h3);
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assign is_inc_rr = (dec_x == 2'h0) & (dec_z == 3'h3) & ~dec_q;
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assign is_dec_rr = (dec_x == 2'h0) & (dec_z == 3'h3) & dec_q;
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assign is_inc_r = (dec_x == 2'h0) & (dec_z == 3'h4);
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assign is_dec_r = (dec_x == 2'h0) & (dec_z == 3'h5);
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assign is_ld_r_n = (dec_x == 2'h0) & (dec_z == 3'h6);
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assign is_ld_rr_a = '0;
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assign is_rla = (dec_x == 3'h0) & (dec_z == 3'h7) & (dec_y == 3'h2);
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assign is_ld_r_r = (dec_x == 2'h1) & ((dec_z != 3'h6) | (dec_y != 3'h6));
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assign is_alu_a_r = (dec_x == 2'h2);
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assign is_pop_rr = (dec_x == 2'h3) & (dec_z == 3'h1) & ~dec_q;
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assign is_push_rr = (dec_x == 2'h3) & (dec_z == 3'h5) & ~dec_q;
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assign is_alu_a_n = (dec_x == 2'h3) & (dec_z == 3'h6);
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assign is_bit_n_r = (is_cb & instr_i[1][7:6] == 2'h1);
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assign is_shift_r = (is_cb & instr_i[1][7:6] == 2'h0) | is_rla;
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assign bus_x_ctrl_o.src = (is_ld_sp_nnnn ) ? BUS_SRC_OPERAND8_H :
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(is_ld_rr_nnnn ) ? BUS_SRC_OPERAND8_H :
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(is_ld_pnnnn_a ) ? BUS_SRC_A :
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(is_ldd_hl_a ) ? BUS_SRC_A :
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(is_ldi_hl_a ) ? BUS_SRC_A :
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(is_ldh_c_a ) ? BUS_SRC_A :
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(is_ldh_n_a ) ? BUS_SRC_A :
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(is_ldh_a_n ) ? BUS_SRC_MEM :
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(is_alu_a_r & (reg8_src == REG8_A )) ? BUS_SRC_A :
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(is_alu_a_r & (reg8_src == REG8_PHL)) ? BUS_SRC_MEM :
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(is_alu_a_r ) ? BUS_SRC_REG8 :
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(is_alu_a_n ) ? BUS_SRC_OPERAND8_L :
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(is_bit_n_r & (reg8_src == REG8_A )) ? BUS_SRC_A :
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(is_bit_n_r & (reg8_src != REG8_A )) ? BUS_SRC_REG8 :
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(is_ld_r_n ) ? BUS_SRC_OPERAND8_L :
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(is_inc_r ) ? BUS_SRC_REG8 :
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(is_dec_r ) ? BUS_SRC_REG8 :
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(is_ld_r_r & (reg8_src == REG8_A )) ? BUS_SRC_A :
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(is_ld_r_r & (reg8_src == REG8_PHL)) ? BUS_SRC_MEM :
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(is_ld_r_r ) ? BUS_SRC_REG8 :
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(is_ld_a_pbc ) ? BUS_SRC_MEM :
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(is_ld_a_pde ) ? BUS_SRC_MEM :
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(is_call_nn & ~is_ex2_i ) ? BUS_SRC_PC_L :
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(is_call_nn & is_ex2_i ) ? BUS_SRC_PC_H :
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(is_push_rr & ~is_ex2_i ) ? BUS_SRC_REG16_L :
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(is_push_rr & is_ex2_i ) ? BUS_SRC_REG16_H :
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(is_pop_rr ) ? BUS_SRC_MEM :
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(is_ret ) ? BUS_SRC_MEM :
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(is_shift_r & (reg8_src == REG8_A )) ? BUS_SRC_A :
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(is_shift_r & (reg8_src != REG8_A )) ? BUS_SRC_REG8 :
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BUS_SRC_MEM;
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assign bus_x_ctrl_o.dst = is_ld_sp_nnnn ? BUS_DST_SP_H :
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is_ld_rr_nnnn ? BUS_DST_REG16_H :
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is_ld_pnnnn_a ? BUS_DST_MEM :
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is_ldd_hl_a ? BUS_DST_MEM :
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is_ldi_hl_a ? BUS_DST_MEM :
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is_ldh_c_a ? BUS_DST_MEM :
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is_ldh_n_a ? BUS_DST_MEM :
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is_ldh_a_n ? BUS_DST_ALU :
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is_alu_a_r ? BUS_DST_ALU :
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is_alu_a_n ? BUS_DST_ALU :
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is_bit_n_r ? BUS_DST_ALU :
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is_inc_r ? BUS_DST_ALU :
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is_dec_r ? BUS_DST_ALU :
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is_ld_a_pbc ? BUS_DST_ALU :
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is_ld_a_pde ? BUS_DST_ALU :
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is_call_nn ? BUS_DST_MEM :
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is_push_rr ? BUS_DST_MEM :
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is_pop_rr & is_ex2_i ? BUS_DST_REG16_H :
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is_pop_rr & is_ex3_i ? BUS_DST_REG16_L :
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is_ret & is_ex2_i ? BUS_DST_PC_H :
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is_ret & is_ex3_i ? BUS_DST_PC_L :
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(is_ld_r_n & (reg8_dest == REG8_A )) ? BUS_DST_ALU :
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(is_ld_r_n & (reg8_dest != REG8_A )) ? BUS_DST_REG8 :
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(is_ld_r_r & (reg8_dest == REG8_A )) ? BUS_DST_ALU :
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(is_ld_r_r & (reg8_dest == REG8_PHL)) ? BUS_DST_MEM :
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(is_ld_r_r ) ? BUS_DST_REG8 :
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(is_shift_r ) ? BUS_DST_ALU :
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BUS_DST_SP_H;
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assign bus_x_ctrl_o.wen =
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is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_n | is_ldd_hl_a |
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is_ldi_hl_a | is_bit_n_r | is_ld_r_n | is_ldh_c_a | is_ldh_n_a | is_ldh_a_n |
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is_call_nn | is_ret | is_push_rr | (is_pop_rr & (is_ex2_i | is_ex3_i)) |
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(is_ret & (is_ex2_i | is_ex3_i)) | is_shift_r | is_inc_r | is_dec_r | is_ld_pnnnn_a |
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(is_ld_r_r & (reg8_src != REG8_PHL)) |
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(is_ld_r_r & (reg8_src == REG8_PHL) & is_ex2_i) |
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(is_alu_a_r & (reg8_src != REG8_PHL)) |
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(is_alu_a_r & (reg8_src == REG8_PHL) & is_ex2_i);
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assign bus_y_ctrl_o.src = is_ld_sp_nnnn ? BUS_SRC_OPERAND8_L :
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is_ld_rr_nnnn ? BUS_SRC_OPERAND8_L :
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is_inc_r ? BUS_SRC_ALU :
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is_dec_r ? BUS_SRC_ALU :
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is_shift_r ? BUS_SRC_ALU :
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is_pop_rr & is_ex2_i ? BUS_SRC_REG16_L :
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is_pop_rr & is_ex3_i ? BUS_SRC_REG16_H :
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is_ret & is_ex2_i ? BUS_SRC_PC_L :
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is_ret & is_ex3_i ? BUS_SRC_PC_H :
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BUS_SRC_MEM;
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assign bus_y_ctrl_o.dst = is_ld_sp_nnnn ? BUS_DST_SP_L :
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is_ld_rr_nnnn ? BUS_DST_REG16_L :
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is_inc_r ? BUS_DST_REG8 :
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is_dec_r ? BUS_DST_REG8 :
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is_shift_r ? BUS_DST_REG8 :
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is_pop_rr & is_ex2_i ? BUS_DST_REG16_L :
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is_pop_rr & is_ex3_i ? BUS_DST_REG16_H :
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is_ret & is_ex2_i ? BUS_DST_PC_L :
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is_ret & is_ex3_i ? BUS_DST_PC_H :
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BUS_DST_REG8;
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assign bus_y_ctrl_o.wen = is_ld_sp_nnnn | is_ld_rr_nnnn | (is_inc_r & reg8_dest != REG8_A) | (is_shift_r & reg8_dest != REG8_A) | (is_dec_r & reg8_dest != REG8_A) | (is_pop_rr & (is_ex2_i | is_ex3_i)) | (is_ret & (is_ex2_i | is_ex3_i));
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assign bus_p_ctrl_o.src = is_ldd_hl_a ? BUS16_SRC_REG16 :
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is_ldi_hl_a ? BUS16_SRC_REG16 :
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is_call_nn ? BUS16_SRC_SP :
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is_ret ? BUS16_SRC_SP :
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is_push_rr ? BUS16_SRC_SP :
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is_pop_rr ? BUS16_SRC_SP :
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is_inc_rr & (reg16_sel == REG16_SP_AF) ? BUS16_SRC_SP :
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is_inc_rr & (reg16_sel != REG16_SP_AF) ? BUS16_SRC_REG16 :
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is_dec_rr & (reg16_sel == REG16_SP_AF) ? BUS16_SRC_SP :
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is_dec_rr & (reg16_sel != REG16_SP_AF) ? BUS16_SRC_REG16 :
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BUS16_SRC_REG16;
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assign bus_p_ctrl_o.dst = BUS16_DST_ALU16;
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assign bus_p_ctrl_o.wen = is_ldd_hl_a | is_ldi_hl_a | is_call_nn | is_ret | is_push_rr | is_pop_rr | is_inc_rr | is_dec_rr;
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assign bus_q_ctrl_o.src = BUS16_SRC_ALU16;
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assign bus_q_ctrl_o.dst = is_ldd_hl_a ? BUS16_DST_REG16 :
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is_ldi_hl_a ? BUS16_DST_REG16 :
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is_call_nn ? BUS16_DST_SP :
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is_ret ? BUS16_DST_SP :
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is_push_rr ? BUS16_DST_SP :
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is_pop_rr ? BUS16_DST_SP :
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is_inc_rr & (reg16_sel == REG16_SP_AF) ? BUS16_DST_SP :
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is_inc_rr & (reg16_sel != REG16_SP_AF) ? BUS16_DST_REG16 :
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is_dec_rr & (reg16_sel == REG16_SP_AF) ? BUS16_DST_SP :
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is_dec_rr & (reg16_sel != REG16_SP_AF) ? BUS16_DST_REG16 :
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BUS16_DST_REG16;
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assign bus_q_ctrl_o.wen = is_ldd_hl_a | is_ldi_hl_a | is_call_nn | (is_ret & (is_ex1_i | is_ex2_i)) | is_push_rr | (is_pop_rr & (is_ex1_i | is_ex2_i)) | is_inc_rr | is_dec_rr;
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assign reg8_src = is_ldh_c_a ? REG8_C :
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is_rla ? REG8_A :
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is_inc_r ? reg8_dest :
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is_dec_r ? reg8_dest :
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is_cb ? reg8_t'(instr_i[1][2:0]) :
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reg8_t'(dec_z);
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assign reg8_dest = is_rla ? REG8_A :
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is_cb ? reg8_t'(instr_i[1][2:0]) :
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reg8_t'(dec_y);
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assign reg16_sel = is_ldd_hl_a ? REG16_HL :
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is_ldi_hl_a ? REG16_HL :
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is_ld_r_r & ((reg8_src == REG8_PHL) | (reg8_dest == REG8_PHL)) ? REG16_HL :
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is_alu_a_r & (reg8_src == REG8_PHL) ? REG16_HL :
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is_ld_a_pbc ? REG16_BC :
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is_ld_a_pde ? REG16_DE :
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reg16_t'(dec_p);
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assign reg8_src_o = reg8_src;
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assign reg8_dest_o = reg8_dest;
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assign reg16_sel_o = reg16_sel;
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assign alu_ctrl_o.alu_op_valid =
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is_alu_a_n |
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(is_alu_a_r & (reg8_src != REG8_PHL)) |
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(is_alu_a_r & (reg8_src == REG8_PHL) & is_ex2_i);
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assign alu_ctrl_o.alu_op = alu_op_t'(dec_y);
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assign alu_ctrl_o.shift_op_valid = is_shift_r;
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assign alu_ctrl_o.shift_op = is_rla ? SHIFT_OP_RL :
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shift_op_t'(instr_i[1][5:3]);
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|
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assign alu_ctrl_o.bsr_op_valid = is_bit_n_r;
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assign alu_ctrl_o.bsr_op.b = is_bit_n_r;
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assign alu_ctrl_o.bsr_op.s = '0;
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assign alu_ctrl_o.bsr_op.r = '0;
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assign alu_ctrl_o.bsr_op.operand = instr_i[1][5:3];
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|
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|
||
|
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assign alu_ctrl_o.incdec_op_valid = is_inc_r | is_dec_r;
|
||
|
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assign alu_ctrl_o.incdec_op.inc = is_inc_r;
|
||
|
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assign alu_ctrl_o.incdec_op.dec = is_dec_r;
|
||
|
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assign alu_ctrl_o.incdec_op.dst_a = reg8_dest == REG8_A;
|
||
|
|
|
||
|
|
assign alu_ctrl_o.update_a =
|
||
|
|
is_alu_a_n |
|
||
|
|
(is_alu_a_r & (reg8_src != REG8_PHL)) |
|
||
|
|
(is_alu_a_r & (reg8_src == REG8_PHL) & is_ex2_i) |
|
||
|
|
(is_ld_r_n & (reg8_dest == REG8_A)) | (is_ld_r_r & (reg8_dest == REG8_A)) |
|
||
|
|
(is_inc_r & (reg8_dest == REG8_A)) | (is_dec_r & (reg8_dest == REG8_A)) |
|
||
|
|
is_ld_a_pbc | is_ld_a_pde | (is_shift_r & (reg8_dest == REG8_A)) |
|
||
|
|
is_ldh_a_n;
|
||
|
|
assign alu_ctrl_o.update_f = is_alu_a_n | is_bit_n_r | is_inc_r | is_dec_r | is_shift_r |
|
||
|
|
(is_alu_a_r & (reg8_src != REG8_PHL)) |
|
||
|
|
(is_alu_a_r & (reg8_src == REG8_PHL) & is_ex2_i);
|
||
|
|
|
||
|
|
assign alu16_inc_o = is_ldi_hl_a | is_ret | is_pop_rr | is_inc_rr;
|
||
|
|
assign alu16_dec_o = is_ldd_hl_a | is_call_nn | is_push_rr | is_dec_rr;
|
||
|
|
|
||
|
|
assign pc_we_o = is_call_nn | (is_ret & (is_ex2_i | is_ex3_i)) | is_jr_nn;
|
||
|
|
assign pc_we_cc_o = is_jr_cc_nn;
|
||
|
|
assign cc_o = cc_t'(dec_y[1:0]);
|
||
|
|
assign pc_src_o = is_ret ? PC_SRC_BUS :
|
||
|
|
is_call_nn ? PC_SRC_OPERAND16 :
|
||
|
|
PC_SRC_OPERAND8;
|
||
|
|
|
||
|
|
assign addr_src_o = is_ldd_hl_a ? ADDR_SRC_REG16 :
|
||
|
|
is_ldi_hl_a ? ADDR_SRC_REG16 :
|
||
|
|
is_ld_a_pbc ? ADDR_SRC_REG16 :
|
||
|
|
is_ld_a_pde ? ADDR_SRC_REG16 :
|
||
|
|
is_ldh_c_a ? ADDR_SRC_REG8 :
|
||
|
|
is_ldh_n_a ? ADDR_SRC_OPERAND8 :
|
||
|
|
is_ldh_a_n ? ADDR_SRC_OPERAND8 :
|
||
|
|
is_call_nn ? ADDR_SRC_SP :
|
||
|
|
is_ret & is_ex3_i ? ADDR_SRC_BUS_P :
|
||
|
|
is_ret ? ADDR_SRC_BUS_Q :
|
||
|
|
is_push_rr ? ADDR_SRC_SP :
|
||
|
|
is_pop_rr & is_ex3_i ? ADDR_SRC_BUS_P :
|
||
|
|
is_pop_rr ? ADDR_SRC_BUS_Q :
|
||
|
|
is_ld_r_r & ((reg8_src == REG8_PHL) | (reg8_dest == REG8_PHL)) ? ADDR_SRC_REG16 :
|
||
|
|
is_alu_a_r & (reg8_src == REG8_PHL) ? ADDR_SRC_REG16 :
|
||
|
|
is_ld_pnnnn_a ? ADDR_SRC_OPERAND16:
|
||
|
|
ADDR_SRC_PC;
|
||
|
|
|
||
|
|
assign instr_undef_o = ~(
|
||
|
|
is_ld_sp_nnnn | is_alu_a_r | is_alu_a_n | is_ld_rr_nnnn | is_ldd_hl_a | is_ldi_hl_a |
|
||
|
|
is_bit_n_r | is_jr_nn | is_jr_cc_nn | is_ld_r_n | is_ldh_c_a | is_inc_r | is_dec_r | is_ld_r_r |
|
||
|
|
is_ldh_n_a | is_ldh_a_n | is_ld_a_pbc | is_ld_a_pde | is_call_nn | is_push_rr | is_pop_rr |
|
||
|
|
(is_shift_r & (instr_i[1][5:3] == 3'h02)) | is_rla | is_inc_rr | is_dec_rr | is_ret |
|
||
|
|
is_ld_pnnnn_a);
|
||
|
|
|
||
|
|
endmodule : idec
|