svgb/rtl/cpu/cpu_pkg.svh

package cpu_pkg;

    //
    // 4  | ST0_ADDR -> ST1_DEC -> ST2_EXEC -> ST3_NOP
    // 12 |                    '-> ST2_DEC  -> ST3_DEC -> ST4_EXEC -> .... -> ST11_NOP
    //
    typedef enum {
        ST0_ADDR,
        ST1_DEC,
        ST2_EXEC,
        ST2_DEC,
        ST3_DEC,
        ST3_EXEC,
        ST4_EXEC
    } state_t;

    typedef enum logic [2:0] {
        REG8_B   = 3'h00,
        REG8_C   = 3'h01,
        REG8_D   = 3'h02,
        REG8_E   = 3'h03,
        REG8_H   = 3'h04,
        REG8_L   = 3'h05,
        REG8_PHL = 3'h06,
        REG8_A   = 3'h07
    } reg8_t;

    typedef enum logic [1:0] {
        REG16_BC    = 2'h00,
        REG16_DE    = 2'h01,
        REG16_HL    = 2'h02,
        REG16_SP_AF = 2'h03
    } reg16_t;

    typedef enum logic [1:0] {
        CC_NZ = 2'h00,
        CC_Z  = 2'h01,
        CC_NC = 2'h02,
        CC_C  = 2'h03
    } cc_t;

    typedef enum logic [3:0] {
        ALU_OP_ADD = 4'h00,
        ALU_OP_ADC = 4'h01,
        ALU_OP_SUB = 4'h02,
        ALU_OP_SBC = 4'h03,
        ALU_OP_AND = 4'h04,
        ALU_OP_XOR = 4'h05,
        ALU_OP_OR  = 4'h06,
        ALU_OP_CP  = 4'h07,
        ALU_OP_BIT = 4'h08,
        ALU_OP_NOP = 4'h09
    } alu_op_t;

    typedef enum logic [1:0] {
        ALU16_OP_ADD = 2'h00,
        ALU16_INC    = 2'h01,
        ALU16_DEC    = 2'h02
    } alu16_op_t;

    typedef enum {
        OP_SRC_A,
        OP_SRC_REG8,
        OP_SRC_OPERAND8,
        OP_SRC_OPERAND16,
        OP_SRC_REG16
    } op_src_t;

    typedef enum {
        OP_DEST_A,
        OP_DEST_REG8,
        OP_DEST_REG16,
        OP_DEST_MEMORY
    } op_dest_t;

    typedef enum {
        SP_SRC_OPERAND16
    } sp_src_t;

    typedef enum {
        ADR_SRC_PC,
        ADR_SRC_HL,
        ADR_SRC_REG8 // extended with FF
    } adr_src_t;

    typedef enum {
        PC_SRC_SEQ,
        PC_SRC_OPERAND8
    } pc_src_t;

endpackage

`define DEF_FF(register, next, we, rst_value) \
    always_ff @(posedge clk_i or negedge nreset_i) begin \
        if (~nreset_i) begin \
            register <= (rst_value); \
        end else if ((we)) begin \
            register <= (next); \
        end \
    end