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49ce1631b3a45d5eee8ef47278f6485204b268b2
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Koray Yanik 49ce1631b3 Implement LD ($FF00+C), A
2021-02-20 22:10:47 +00:00
build
Initial register bank, support LD RR, $nnnn instructions
2021-02-17 22:40:24 +00:00
rtl
Implement LD ($FF00+C), A
2021-02-20 22:10:47 +00:00
sim
Implement LD ($FF00+C), A
2021-02-20 22:10:47 +00:00
synthflow @ 767277e341
Initial work on build system
2021-02-15 21:40:12 +00:00
.gitignore
Initial work on decoder
2021-02-16 21:13:50 +00:00
.gitmodules
Initial work on build system
2021-02-15 21:40:12 +00:00
README.md
Initial commit
2021-02-15 14:54:08 +01:00

README.md

svgb

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Description
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Readme 122 KiB
Languages
SystemVerilog 88%
C 11.5%
Makefile 0.5%