19 lines
245 B
Systemverilog
19 lines
245 B
Systemverilog
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module clkgen #(
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PERIOD_NS = 10,
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RESET_DELAY_NS = 45
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) (
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output logic clk,
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output logic nreset
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);
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initial begin
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clk <= 1'b1;
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nreset <= 1'b0;
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#RESET_DELAY_NS nreset <= 1'b1;
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end
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always
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#(PERIOD_NS/2) clk <= ~clk;
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endmodule
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