svgb/build/tb_top.Makefile

TB       = tb_top
SOURCES  = gb.sv cpu.sv alu.sv registers.sv control.sv decode.sv rom.sv tb_top.sv clkgen.sv
PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared

gb.sdb:  cpu.sdb rom.sdb cpu_pkg.sdb
cpu.sdb: control.sdb registers.sdb alu.sdb  cpu_pkg.sdb
control.sdb: decode.sdb cpu_pkg.sdb
alu.sdb: cpu_pkg.sdb
registers.sdb: cpu_pkg.sdb

include ../synthflow/vivado/Makefile.rules
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00			`TB = tb_top`
Implemented SP, $nnnn and XOR A instructions 2021-02-17 00:05:46 +01:00			`SOURCES = gb.sv cpu.sv alu.sv registers.sv control.sv decode.sv rom.sv tb_top.sv clkgen.sv`
Initial work on reading instructions from bootROM 2021-02-15 23:55:09 +01:00			`PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared`

Initial register bank, support LD RR, $nnnn instructions 2021-02-17 23:40:24 +01:00			`gb.sdb: cpu.sdb rom.sdb cpu_pkg.sdb`
			`cpu.sdb: control.sdb registers.sdb alu.sdb cpu_pkg.sdb`
			`control.sdb: decode.sdb cpu_pkg.sdb`
			`alu.sdb: cpu_pkg.sdb`
			`registers.sdb: cpu_pkg.sdb`
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00
			`include ../synthflow/vivado/Makefile.rules`