svgb/build/tb_top.Makefile

TB       = tb_top
SOURCES  = gb.sv cpu.sv registers.sv control.sv decode.sv rom.sv tb_top.sv clkgen.sv
PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared

gb.sdb:  cpu.sdb rom.sdb
cpu.sdb: control.sdb fetch.sdb registers.sdb

include ../synthflow/vivado/Makefile.rules
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00			`TB = tb_top`
Initial work on decoder Decode the LD SP, $nnnn instruction as our first three-byte instruction. 2021-02-16 22:13:50 +01:00			`SOURCES = gb.sv cpu.sv registers.sv control.sv decode.sv rom.sv tb_top.sv clkgen.sv`
Initial work on reading instructions from bootROM 2021-02-15 23:55:09 +01:00			`PATH_SRC = ../rtl:../rtl/cpu:../rtl/shared:../sim/tbench:../sim/shared`

			`gb.sdb: cpu.sdb rom.sdb`
			`cpu.sdb: control.sdb fetch.sdb registers.sdb`
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00
			`include ../synthflow/vivado/Makefile.rules`