svgb/rtl/ram.sv

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Systemverilog
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module ram #(
parameter DATA_W = 8,
parameter ADDR_W = 8
)(
input logic clk,
input logic nreset,
input logic cs_i,
input logic [ADDR_W-1:0] address_i,
input logic we_i,
input logic [DATA_W-1:0] wdata_i,
output logic [DATA_W-1:0] rdata_o
);
localparam RAM_SIZE = 2**ADDR_W;
logic [DATA_W-1:0] ram [RAM_SIZE-1:0];
logic [DATA_W-1:0] rdata;
logic we;
assign we = cs_i & we_i;
always_ff @(posedge clk) begin
if (we)
ram[address_i] <= wdata_i;
end
always_ff @(posedge clk or negedge nreset) begin
if (!nreset)
rdata <= '0;
else
rdata <= ram[address_i];
end
assign rdata_o = {8{cs_i}} & rdata;
endmodule