Add chip selects to rom/ram

Slightly easier to work with ppu and cart memory spaces this way
This commit is contained in:
Koray Yanik 2023-10-02 21:23:39 +01:00
parent fda176d3b5
commit 5f98c7346f
4 changed files with 44 additions and 29 deletions

View File

@ -26,11 +26,9 @@ logic rom_sel;
logic [ 7:0] rom_rdata;
logic hiram_sel;
logic hiram_we;
logic [ 7:0] hiram_rdata;
logic vram_sel;
logic vram_we;
logic [ 7:0] vram_rdata;
cpu cpu_inst (
@ -50,8 +48,7 @@ ppu ppu_inst (
.cpu_addr_i (cpu_addr),
.cpu_rdata_o(cpu_ppu_rdata),
.cpu_we_i (cpu_we),
.cpu_wdata_i(cpu_wdata),
.cpu_addr_sel_o(ppu_sel)
.cpu_wdata_i(cpu_wdata)
);
assign rom_enable_r = '1;
@ -60,13 +57,10 @@ assign rom_sel = rom_enable_r & ~(|cpu_addr[15:8]);
assign vram_sel = (cpu_addr[15:13] == 3'b100);
assign hiram_sel = (&cpu_addr[15:7]) & ~(&cpu_addr[6:0]);
assign vram_we = vram_sel & cpu_we;
assign hiram_we = hiram_sel & cpu_we;
assign cpu_rdata = ({8{ rom_sel}} & rom_rdata) |
({8{ vram_sel}} & vram_rdata) |
({8{hiram_sel}} & hiram_rdata)|
({8{ ppu_sel}} & cpu_ppu_rdata);
assign cpu_rdata = rom_rdata |
vram_rdata |
hiram_rdata |
cpu_ppu_rdata;
rom #(
.FILE_NAME("DMG_ROM.bin"),
@ -74,6 +68,8 @@ rom #(
.DATA_W (8)
) rom_inst (
.clk (clk),
.nreset (nreset),
.cs_i (rom_sel),
.address_i(cpu_addr[7:0]),
.rdata_o (rom_rdata)
);
@ -83,9 +79,11 @@ ram #(
.DATA_W (8)
) vram_inst (
.clk (clk),
.nreset (nreset),
.cs_i (vram_sel),
.address_i (cpu_addr[12:0]),
.rdata_o (vram_rdata),
.we_i (vram_we),
.we_i (cpu_we),
.wdata_i (cpu_wdata)
);
@ -94,9 +92,11 @@ ram #(
.DATA_W (8)
) hiram_inst (
.clk (clk),
.nreset (nreset),
.cs_i (hiram_sel),
.address_i (cpu_addr[6:0]),
.rdata_o (hiram_rdata),
.we_i (hiram_we),
.we_i (cpu_we),
.wdata_i (cpu_wdata)
);

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@ -5,15 +5,12 @@ module ppu (
input logic [15:0] cpu_addr_i,
output logic [ 7:0] cpu_rdata_o,
input logic cpu_we_i,
input logic [ 7:0] cpu_wdata_i,
output logic cpu_addr_sel_o
input logic [ 7:0] cpu_wdata_i
);
logic ly_sel;
logic ly_r;
logic ly_we;
logic ly_sel;
logic [ 7:0] ly_r;
logic ly_we;
assign ly_sel = (cpu_addr_i == 16'hFF44);
assign ly_we = ly_sel & cpu_we_i;
@ -25,6 +22,6 @@ always_ff @(posedge clk or negedge nreset) begin
ly_r <= 8'h90;
end
assign cpu_addr_sel_o = ly_sel;
assign cpu_rdata_o = {8{ly_sel}} & ly_r;
endmodule : ppu

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@ -3,7 +3,9 @@ module ram #(
parameter ADDR_W = 8
)(
input logic clk,
input logic nreset,
input logic cs_i,
input logic [ADDR_W-1:0] address_i,
input logic we_i,
input logic [DATA_W-1:0] wdata_i,
@ -16,13 +18,22 @@ logic [DATA_W-1:0] ram [RAM_SIZE-1:0];
logic [DATA_W-1:0] rdata;
always_ff @(posedge clk)
if (we_i)
logic we;
assign we = cs_i & we_i;
always_ff @(posedge clk) begin
if (we)
ram[address_i] <= wdata_i;
end
always_ff @(posedge clk)
rdata <= ram[address_i];
always_ff @(posedge clk or negedge nreset) begin
if (!nreset)
rdata <= '0;
else
rdata <= ram[address_i];
end
assign rdata_o = rdata;
assign rdata_o = {8{cs_i}} & rdata;
endmodule

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@ -4,6 +4,9 @@ module rom #(
parameter integer unsigned DATA_W = 8
) (
input logic clk,
input logic nreset,
input logic cs_i,
input logic [ADDR_W-1:0] address_i,
output logic [DATA_W-1:0] rdata_o
);
@ -13,10 +16,14 @@ localparam ROM_SIZE = 2**ADDR_W;
logic [DATA_W-1:0] rom [ROM_SIZE-1:0];
logic [DATA_W-1:0] rdata;
always_ff @(posedge clk)
rdata <= rom[address_i];
always_ff @(posedge clk or negedge nreset) begin
if (!nreset)
rdata <= '0;
else
rdata <= rom[address_i];
end
assign rdata_o = rdata;
assign rdata_o = {8{cs_i}} & rdata;
initial begin
static integer fd = $fopen(FILE_NAME, "rb");