svgb/rtl/rom.sv

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Systemverilog
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module rom #(
parameter string FILE_NAME = "",
parameter integer unsigned ADDR_W = 8,
parameter integer unsigned DATA_W = 8
) (
input logic clk,
input logic nreset,
input logic cs_i,
input logic [ADDR_W-1:0] address_i,
output logic [DATA_W-1:0] rdata_o
);
localparam ROM_SIZE = 2**ADDR_W;
logic [DATA_W-1:0] rom [ROM_SIZE-1:0];
logic [DATA_W-1:0] rdata;
always_ff @(posedge clk or negedge nreset) begin
if (!nreset)
rdata <= '0;
else
rdata <= rom[address_i];
end
assign rdata_o = {8{cs_i}} & rdata;
initial begin
static integer fd = $fopen(FILE_NAME, "rb");
static integer rv = $fread(rom, fd);
end
endmodule : rom