31 lines
534 B
Systemverilog
31 lines
534 B
Systemverilog
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module cart (
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input wire clk,
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input wire nreset,
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input wire nrd_i,
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input wire nwr_i,
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input wire ncs_i,
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input wire [15:0] addr_i,
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inout wire [ 7:0] data_io
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);
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logic cs;
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logic [ 7:0] rom_rdata;
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assign cs = ~ncs_i;
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assign data_io = (cs & ~nrd_i) ? rom_rdata : 'Z;
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rom #(
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.FILE_NAME("tetris.gb"),
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.ADDR_W (14),
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.DATA_W (8)
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) rom_inst (
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.clk (clk),
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.nreset (nreset),
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.cs_i (cs),
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.address_i(addr_i[13:0]),
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.rdata_o (rom_rdata)
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);
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endmodule : cart
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