svgb/rtl/gb.sv

module gb (
    input  logic clk_i,
    input  logic nreset_i
);

    logic        we;
    logic [15:0] address;
    logic [ 7:0] rdata;
    logic [ 7:0] wdata;

    cpu cpu_inst (
        .clk_i    (clk_i),
        .nreset_i (nreset_i),
        .address_o(address),
        .rdata_i  (rdata),
        .we_o     (we),
        .wdata_o  (wdata)
    );

    rom #(
        .FILE_NAME("DMG_ROM.bin"),
        .ADDR_W   (8),
        .DATA_W   (8)
    ) rom_inst (
        .clk_i    (clk_i),
        .address_i(address[7:0]),
        .rdata_o  (rdata)
    );

endmodule : gb