Implemented SP, $nnnn and XOR A instructions

rtl/cpu/alu.sv

@@ -0,0 +1,54 @@
+`include "cpu_pkg.svh"
+
+import cpu_pkg::*;
+
+module alu (
+    input logic       clk_i,
+    input logic       nreset_i,
+
+    input logic       alu_op_valid_i,
+    input alu_op_t    alu_op_i,
+    input logic [7:0] operand_i,
+
+    output logic [ 7:0] a_o,
+    output logic [ 7:0] f_o
+);
+
+    logic        a_we;
+    logic [ 7:0] a_r;
+    logic [ 7:0] a_next;
+
+    logic        f_we;
+    logic [ 7:0] f_r;
+    logic [ 7:0] f_next;
+
+    logic [ 7:0] a_xor;
+    logic [ 7:0] f_xor;
+
+    `define DEF_FF(register, next, we, rst_value) \
+        always_ff @(posedge clk_i or negedge nreset_i) begin \
+            if (~nreset_i) begin \
+                register <= (rst_value); \
+            end else if ((we)) begin \
+                register <= (next); \
+            end \
+        end
+
+    `DEF_FF(a_r, a_next, a_we, '0);
+    `DEF_FF(f_r, f_next, f_we, '0);
+
+    assign a_we   = alu_op_valid_i;
+    assign a_next = (alu_op_i == ALU_OP_XOR) ? a_xor :
+                                               a_xor;
+
+    assign f_we   = alu_op_valid_i;
+    assign f_next = (alu_op_i == ALU_OP_XOR) ? f_xor :
+                                               f_xor;
+
+    assign a_xor = (a_r ^ operand_i);
+    assign f_xor = {~(|a_xor), 3'b0, f_r[3:0]};
+
+    assign a_o = a_r;
+    assign f_o = f_r;
+
+endmodule : alu