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svgb
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SystemVerilog 88%
C 11.5%
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Koray Yanik 237a5f1489 Implemented SP, $nnnn and XOR A instructions 2021-02-16 23:05:46 +00:00
build Implemented SP, $nnnn and XOR A instructions 2021-02-16 23:05:46 +00:00
rtl Implemented SP, $nnnn and XOR A instructions 2021-02-16 23:05:46 +00:00
sim Initial work on decoder 2021-02-16 21:13:50 +00:00
synthflow@767277e341 Initial work on build system 2021-02-15 21:40:12 +00:00
.gitignore Initial work on decoder 2021-02-16 21:13:50 +00:00
.gitmodules Initial work on build system 2021-02-15 21:40:12 +00:00
README.md Initial commit 2021-02-15 14:54:08 +01:00

README.md

svgb