Starting work on PPU -> display -> VGA

rtl/ppu/ppu.sv

@@ -4,10 +4,16 @@ module ppu (
   input  logic clk,
   input  logic nreset,
 
+  output logic        display_enable_o,
+
   input  logic [15:0] cpu_addr_i,
   output logic [ 7:0] cpu_rdata_o,
   input  logic        cpu_we_i,
-  input  logic [ 7:0] cpu_wdata_i
+  input  logic [ 7:0] cpu_wdata_i,
+
+  output logic [ 1:0] pixel_o,
+  output logic        vsync_o,
+  output logic        hsync_o
 );
 
 `define IOREG_DECL(name)    \
@@ -24,7 +30,7 @@ module ppu (
       name``_r <= name``_next; \
   end \
   assign name``_sel = (cpu_addr_i == addr); \
-  assign name``_we  = name``_we & cpu_we_i;
+  assign name``_we  = name``_sel & cpu_we_i;
 
 typedef struct packed {
   logic lcd_en;
@@ -93,6 +99,14 @@ assign cpu_rdata_o =
 `endif
   {8{  sy_sel}} &   sy_r;
 
+assign pixel_o = ((lx_r < 8'd160) & (ly_r  < 8'd144)) ? ly_r[1:0] : // should create a nice line-pattern for now
+                                                        2'h00;
+
+assign vsync_o = ly_r >= 8'd144;
+assign hsync_o = lx_r >= 8'd160;
+
+assign display_enable_o = lcdc_r[7];
+
 `undef IOREG_DEF
 `undef IOREG_DECL