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fumyuun
3c3dbd2175
Starting work on PPU -> display -> VGA
2023-10-13 20:46:05 +01:00
build
Starting work on PPU -> display -> VGA
2023-10-13 20:46:05 +01:00
dpi
Starting work on PPU -> display -> VGA
2023-10-13 20:46:05 +01:00
rtl
Starting work on PPU -> display -> VGA
2023-10-13 20:46:05 +01:00
sim
Starting work on PPU -> display -> VGA
2023-10-13 20:46:05 +01:00
src
Starting work on PPU -> display -> VGA
2023-10-13 20:46:05 +01:00
synthflow
@
cc619981f0
Starting work on PPU -> display -> VGA
2023-10-13 20:46:05 +01:00
.gitignore
Complete rewrite from scratch, bootstrap WIP
2023-10-01 23:00:56 +01:00
.gitmodules
Initial work on build system
2021-02-15 21:40:12 +00:00
README.md
Initial commit
2021-02-15 14:54:08 +01:00
README.md
svgb
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Readme
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SystemVerilog
88%
C
11.5%
Makefile
0.5%
