Implemented LDD (HL), A

rtl/cpu/alu.sv

@@ -10,8 +10,14 @@ module alu (
     input alu_op_t    alu_op_i,
     input logic [7:0] operand_i,
 
+    input alu16_op_t   alu16_op_i,
+    input logic [15:0] inx16_i,
+    input logic [15:0] iny16_i,
+
     output logic [ 7:0] a_o,
-    output logic [ 7:0] f_o
+    output logic [ 7:0] f_o,
+
+    output logic [15:0] out16_o
 );
 
     logic        a_we;
@@ -25,6 +31,11 @@ module alu (
     logic [ 7:0] a_xor;
     logic [ 7:0] f_xor;
 
+    logic [16:0] out16_add;
+    logic [ 7:0] f16_add;
+    logic [15:0] out16_inc;
+    logic [15:0] out16_dec;
+
     `DEF_FF(a_r, a_next, a_we, '0);
     `DEF_FF(f_r, f_next, f_we, '0);
 
@@ -39,7 +50,11 @@ module alu (
     assign a_xor = (a_r ^ operand_i);
     assign f_xor = {~(|a_xor), 3'b0, f_r[3:0]};
 
+    assign out16_dec = (inx16_i - 16'h01);
+
     assign a_o = a_r;
     assign f_o = f_r;
 
+    assign out16_o = out16_dec;
+
 endmodule : alu