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Koray Yanik 8f0b8d3a48 Implemented LDD (HL), A 2021-02-18 23:22:26 +00:00
build Initial register bank, support LD RR, $nnnn instructions 2021-02-17 22:40:24 +00:00
rtl Implemented LDD (HL), A 2021-02-18 23:22:26 +00:00
sim Initial register bank, support LD RR, $nnnn instructions 2021-02-17 22:40:24 +00:00
synthflow@767277e341 Initial work on build system 2021-02-15 21:40:12 +00:00
.gitignore Initial work on decoder 2021-02-16 21:13:50 +00:00
.gitmodules Initial work on build system 2021-02-15 21:40:12 +00:00
README.md Initial commit 2021-02-15 14:54:08 +01:00

README.md

svgb