Fix some verilog issues

2023-10-03 22:30:36 +01:00
parent 06746f71fb
commit 9cc63a248e
8 changed files with 25 additions and 18 deletions
--- a/rtl/gb.sv
+++ b/rtl/gb.sv
@@ -114,4 +114,4 @@ assign cart_nwr_o    = 1'b1;
 assign cart_ncs_o    = ~cart_sel;
 assign cart_addr_o   = cpu_addr;

-endmodule : gb
+endmodule : gb