Fix some verilog issues

rtl/ppu/ppu.sv

@@ -1,3 +1,5 @@
+`define VSYNC_HACK
+
 module ppu (
   input  logic clk,
   input  logic nreset,
@@ -77,14 +79,18 @@ assign ly_next = (ly_sel & cpu_we_i)                 ? 8'h00 : // Clear on write
                  (lx_end_of_line & ~ly_end_of_frame) ? (ly_r + 8'h01) :
                                                         ly_r;
 
-assign lx_next = lx_end_of_line ? 8'h0 : (lx_r + 8'h01);
+assign lx_next = lx_end_of_line ? 9'h0 : (lx_r + 9'h01);
 
 assign ly_end_of_frame = ly_r > 8'd153;
 assign lx_end_of_line  = lx_r > 9'd456;
 
 assign cpu_rdata_o =
   {8{lcdc_sel}} & lcdc_r |
+`ifdef VSYNC_HACK
+  {8{  ly_sel}} &   8'h90 |
+`else
   {8{  ly_sel}} &   ly_r |
+`endif
   {8{  sy_sel}} &   sy_r;
 
 `undef IOREG_DEF