Fix some verilog issues

2023-10-03 22:30:36 +01:00
parent 06746f71fb
commit 9cc63a248e
8 changed files with 25 additions and 18 deletions
--- a/sim/clkgen.sv
+++ b/sim/clkgen.sv
@@ -7,9 +7,9 @@ RESET_DELAY_NS = 45
 );

 initial begin
-  clk    <= 1'b1;
-  nreset <= 1'b0;
-  #RESET_DELAY_NS nreset <= 1'b1;
+  clk    = 1'b1;
+  nreset = 1'b0;
+  #RESET_DELAY_NS nreset = 1'b1;
 end

 always