Complete rewrite from scratch, bootstrap WIP

Rewrite to use several bus multiplexers, resulting into a less messy
microarchitecture (hopefully). Some more room for cleanup though...

Supports every instruction from the bootstrap rom, more or less.
LY hacked at 0x90 to progress through vsync instantly.
No cartridge is present yet, so we will always fail checksum test and lock up.

rtl/gb.sv

@@ -1,54 +1,105 @@
+// Top level gb module
 module gb (
-    input  logic clk_i,
-    input  logic nreset_i
+  input  logic clk,
+  input  logic nreset,
+
+  // Cartridge bus
+  output  logic        cart_clk_o,
+  output  logic        cart_nreset_o,
+  output  logic        cart_nrd_o,
+  output  logic        cart_nwr_o,
+  output  logic        cart_ncs_o,
+  output  logic [15:0] cart_addr_o,
+  input   logic [ 7:0] cart_data_i
+
 );
 
-    logic        we;
-    logic [15:0] address;
-    logic [ 7:0] rdata;
-    logic [ 7:0] wdata;
+logic [15:0] cpu_addr;
+logic [ 7:0] cpu_rdata;
+logic        cpu_we;
+logic [ 7:0] cpu_wdata;
 
-    logic        rom_cs;
-    logic [ 7:0] rom_rdata;
+logic [ 7:0] cpu_ppu_rdata;
 
-    logic        hi_ram_cs;
-    logic [ 7:0] hi_ram_rdata;
+logic        rom_enable_r;
+logic        rom_sel;
+logic [ 7:0] rom_rdata;
 
-    cpu cpu_inst (
-        .clk_i    (clk_i),
-        .nreset_i (nreset_i),
-        .address_o(address),
-        .rdata_i  (rdata),
-        .we_o     (we),
-        .wdata_o  (wdata)
-    );
+logic        hiram_sel;
+logic        hiram_we;
+logic [ 7:0] hiram_rdata;
 
-    rom #(
-        .FILE_NAME("DMG_ROM.bin"),
-        .ADDR_W   (8),
-        .DATA_W   (8)
-    ) rom_inst (
-        .clk_i    (clk_i),
-        .cs_i     (rom_cs),
-        .address_i(address[7:0]),
-        .rdata_o  (rom_rdata)
-    );
+logic        vram_sel;
+logic        vram_we;
+logic [ 7:0] vram_rdata;
 
-    ram #(
-        .ADDR_W (7),
-        .DATA_W (8)
-    ) hi_ram_inst (
-        .clk_i     (clk_i),
-        .cs_i      (hi_ram_cs),
-        .address_i (address[6:0]),
-        .rdata_o   (hi_ram_rdata),
-        .we_i      (we),
-        .wdata_i   (wdata)
-    );
+cpu cpu_inst (
+  .clk    (clk),
+  .nreset (nreset),
 
-    assign rom_cs    = ~(|address[15:8]);
-    assign hi_ram_cs = (&address[15:7]) & ~(&address[6:0]);
+  .addr_o (cpu_addr),
+  .rdata_i(cpu_rdata),
+  .we_o   (cpu_we),
+  .wdata_o(cpu_wdata)
+);
 
-    assign rdata = rom_rdata | hi_ram_rdata;
+ppu ppu_inst (
+  .clk    (clk),
+  .nreset (nreset),
 
-endmodule : gb
+  .cpu_addr_i (cpu_addr),
+  .cpu_rdata_o(cpu_ppu_rdata),
+  .cpu_we_i   (cpu_we),
+  .cpu_wdata_i(cpu_wdata),
+  .cpu_addr_sel_o(ppu_sel)
+);
+
+assign rom_enable_r = '1;
+
+assign rom_sel   = rom_enable_r & ~(|cpu_addr[15:8]);
+assign vram_sel  = (cpu_addr[15:13] == 3'b100);
+assign hiram_sel = (&cpu_addr[15:7]) & ~(&cpu_addr[6:0]);
+
+assign vram_we  = vram_sel  & cpu_we;
+assign hiram_we = hiram_sel & cpu_we;
+
+assign cpu_rdata = ({8{  rom_sel}} & rom_rdata)  |
+                   ({8{ vram_sel}} & vram_rdata) |
+                   ({8{hiram_sel}} & hiram_rdata)|
+                   ({8{  ppu_sel}} & cpu_ppu_rdata);
+
+rom #(
+  .FILE_NAME("DMG_ROM.bin"),
+  .ADDR_W   (8),
+  .DATA_W   (8)
+) rom_inst (
+  .clk      (clk),
+  .address_i(cpu_addr[7:0]),
+  .rdata_o  (rom_rdata)
+);
+
+ram #(
+  .ADDR_W   (13),
+  .DATA_W   (8)
+) vram_inst (
+  .clk       (clk),
+  .address_i (cpu_addr[12:0]),
+  .rdata_o   (vram_rdata),
+  .we_i      (vram_we),
+  .wdata_i   (cpu_wdata)
+);
+
+ram #(
+  .ADDR_W (7),
+  .DATA_W (8)
+) hiram_inst (
+  .clk       (clk),
+  .address_i (cpu_addr[6:0]),
+  .rdata_o   (hiram_rdata),
+  .we_i      (hiram_we),
+  .wdata_i   (cpu_wdata)
+);
+
+
+
+endmodule : gb