40 lines
715 B
Systemverilog
40 lines
715 B
Systemverilog
module ram #(
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parameter DATA_W = 8,
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parameter ADDR_W = 8
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)(
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input logic clk,
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input logic nreset,
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input logic cs_i,
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input logic [ADDR_W-1:0] address_i,
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input logic we_i,
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input logic [DATA_W-1:0] wdata_i,
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output logic [DATA_W-1:0] rdata_o
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);
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localparam RAM_SIZE = 2**ADDR_W;
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logic [DATA_W-1:0] ram [RAM_SIZE-1:0];
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logic [DATA_W-1:0] rdata;
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logic we;
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assign we = cs_i & we_i;
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always_ff @(posedge clk) begin
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if (we)
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ram[address_i] <= wdata_i;
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end
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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rdata <= '0;
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else
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rdata <= ram[address_i];
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end
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assign rdata_o = {8{cs_i}} & rdata;
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endmodule
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