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06746f71fb9bc05405ec44c43c47f49958e5e0bd
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Koray Yanik 06746f71fb WIP PPU LX/LY registers 
Removed second reg16 read port - no longer needed.
2023-10-03 20:44:28 +01:00
build
WIP PPU LX/LY registers
2023-10-03 20:44:28 +01:00
rtl
WIP PPU LX/LY registers
2023-10-03 20:44:28 +01:00
sim
WIP on PPU io registers
2023-10-02 22:47:32 +01:00
synthflow @ 1486728ced
Complete rewrite from scratch, bootstrap WIP
2023-10-01 23:00:56 +01:00
.gitignore
Complete rewrite from scratch, bootstrap WIP
2023-10-01 23:00:56 +01:00
.gitmodules
Initial work on build system
2021-02-15 21:40:12 +00:00
README.md
Initial commit
2021-02-15 14:54:08 +01:00

README.md

svgb

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Description
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Readme 122 KiB
Languages
SystemVerilog 88%
C 11.5%
Makefile 0.5%