62 lines
1.3 KiB
Systemverilog
62 lines
1.3 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module cpu (
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input logic clk_i,
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input logic nreset_i,
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output logic [15:0] address_o,
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input logic [ 7:0] rdata_i
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);
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state_t state;
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logic alu_op_valid;
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alu_op_t alu_op;
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op_src_t op_src;
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op_dest_t op_dest;
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logic [ 7:0] alu_operand;
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logic [ 7:0] rega;
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logic [ 7:0] regf;
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logic [15:0] pc;
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logic [15:0] sp;
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control control_inst (
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.clk_i (clk_i),
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.nreset_i (nreset_i),
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.rdata_i (rdata_i),
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.state_o (state),
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.pc_o (pc),
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.sp_o (sp),
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.alu_op_valid_o(alu_op_valid),
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.alu_op_o (alu_op),
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.op_src_o (op_src),
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.op_dest_o (op_dest)
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);
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alu alu_inst (
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.clk_i (clk_i),
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.nreset_i (nreset_i),
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.alu_op_valid_i(alu_op_valid),
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.alu_op_i (alu_op),
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.operand_i (alu_operand),
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.a_o (rega),
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.f_o (regf)
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);
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registers registers_inst (
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.clk_i (clk_i),
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.nreset_i(nreset_i)
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);
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assign alu_operand = (op_src == OP_SRC_A) ? rega :
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'0;
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assign address_o = pc;
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endmodule : cpu
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