50 lines
1.0 KiB
Systemverilog
50 lines
1.0 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module control (
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input logic clk_i,
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input logic nreset_i,
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output state_t state_o,
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output logic [15:0] pc_o
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);
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state_t state_r;
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state_t state_next;
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logic pc_we;
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logic [15:0] pc_r;
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logic [15:0] pc_next;
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always_ff @(posedge clk_i or negedge nreset_i) begin
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if (~nreset_i)
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state_r <= ST0_ADDR;
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else
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state_r <= state_next;
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end
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always_ff @(posedge clk_i or negedge nreset_i) begin
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if (~nreset_i)
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pc_r <= '0;
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else if (pc_we)
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pc_r <= pc_next;
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end
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assign pc_we = (state_r == ST0_ADDR);
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assign pc_next = (pc_r + 16'b1);
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always_comb begin
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case (state_r)
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ST0_ADDR: state_next = ST1_DEC;
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ST1_DEC: state_next = ST2_EXEC;
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ST2_EXEC: state_next = ST3_INC_ADDR;
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ST3_INC_ADDR: state_next = ST0_ADDR;
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endcase
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end
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assign state_o = state_r;
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assign pc_o = pc_r;
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endmodule : control
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