svgb/sim/tbench/tb_top.sv

46 lines
1.1 KiB
Systemverilog

module tb_top ();
logic clk;
logic nreset;
clkgen clkgen_inst (
.clk_o (clk),
.nreset_o(nreset)
);
gb gb_inst (
.clk_i (clk),
.nreset_i(nreset)
);
// Testbench code
logic instr_undef;
logic halted;
logic [15:0] last_pc;
logic [ 7:0] last_opcode;
logic we;
logic [15:0] address;
logic [ 7:0] wdata;
assign halted = gb_inst.cpu_inst.control_inst.halted_r;
assign instr_undef = gb_inst.cpu_inst.control_inst.is_undef;
assign last_pc = gb_inst.cpu_inst.control_inst.instr_pc_r;
assign last_opcode = gb_inst.cpu_inst.control_inst.instr_r;
assign we = gb_inst.we;
assign address = gb_inst.address;
assign wdata = gb_inst.wdata;
always @(posedge clk) begin
if (nreset && instr_undef & ~halted) begin
$display($sformatf("[%t] %X: Undefined opcode %X", $time(), last_pc, last_opcode));
$fatal(0);
end
if (nreset && we) begin
$display($sformatf("[%t] Write: [%X] <= %X", $time(), address, wdata));
end
end
endmodule : tb_top