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67361093ecbca3311188bbd9b2e169acce3912b7
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Koray Yanik 67361093ec Implement LD r, $nn
2021-02-20 15:56:22 +00:00
build
Initial register bank, support LD RR, $nnnn instructions
2021-02-17 22:40:24 +00:00
rtl
Implement LD r, $nn
2021-02-20 15:56:22 +00:00
sim
Initial register bank, support LD RR, $nnnn instructions
2021-02-17 22:40:24 +00:00
synthflow @ 767277e341
Initial work on build system
2021-02-15 21:40:12 +00:00
.gitignore
Initial work on decoder
2021-02-16 21:13:50 +00:00
.gitmodules
Initial work on build system
2021-02-15 21:40:12 +00:00
README.md
Initial commit
2021-02-15 14:54:08 +01:00

README.md

svgb

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Description
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Readme 122 KiB
Languages
SystemVerilog 88%
C 11.5%
Makefile 0.5%