170 lines
4.9 KiB
Systemverilog
170 lines
4.9 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module alu (
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input logic clk,
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input logic nreset,
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input alu_ctrl_t alu_ctrl_i,
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input logic [ 7:0] operand_in_i,
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output logic [ 7:0] operand_out_o,
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output logic [ 7:0] reg_a_o,
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output logic [ 7:0] reg_f_o
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);
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logic nop_valid;
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logic a_we;
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logic [ 7:0] a_r;
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logic [ 7:0] a_next;
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logic f_we;
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logic [ 7:0] f_r;
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logic [ 7:0] f_next;
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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a_r <= '0;
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else if (a_we)
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a_r <= a_next;
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end
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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f_r <= '0;
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else if (f_we)
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f_r <= f_next;
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end
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assign a_we = alu_ctrl_i.update_a;
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assign f_we = alu_ctrl_i.update_f;
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assign reg_a_o = a_r;
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assign reg_f_o = f_r;
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logic [ 7:0] alu_a;
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logic [ 7:0] alu_f;
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logic [ 7:0] shift_a;
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logic [ 7:0] shift_f;
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logic [ 7:0] bsr_a;
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logic [ 7:0] bsr_f;
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logic [ 7:0] incdec_a;
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logic [ 7:0] incdec_f;
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assign nop_valid = ~alu_ctrl_i.alu_op_valid &
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~alu_ctrl_i.shift_op_valid &
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~alu_ctrl_i.bsr_op_valid &
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~alu_ctrl_i.incdec_op_valid;
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assign a_next = ({8{alu_ctrl_i.alu_op_valid }} & alu_a) |
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({8{alu_ctrl_i.shift_op_valid }} & shift_a) |
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({8{alu_ctrl_i.bsr_op_valid }} & bsr_a) |
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({8{alu_ctrl_i.incdec_op_valid}} & incdec_a) |
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({8{nop_valid }} & operand_in_i);
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assign f_next = ({8{alu_ctrl_i.alu_op_valid }} & alu_f) |
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({8{alu_ctrl_i.shift_op_valid }} & shift_f) |
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({8{alu_ctrl_i.bsr_op_valid }} & bsr_f) |
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({8{alu_ctrl_i.incdec_op_valid}} & incdec_f) |
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({8{nop_valid }} & operand_in_i);
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logic [ 8:0] add_a;
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logic [ 7:0] add_f;
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logic [ 8:0] sub_a;
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logic [ 7:0] sub_f;
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logic [ 7:0] xor_a;
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logic [ 7:0] xor_f;
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logic [ 7:0] cp_a;
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logic [ 7:0] cp_f;
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assign alu_a = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_a[7:0]) |
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({8{alu_ctrl_i.alu_op == ALU_OP_SUB}} & sub_a[7:0]) |
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({8{alu_ctrl_i.alu_op == ALU_OP_XOR}} & xor_a) |
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({8{alu_ctrl_i.alu_op == ALU_OP_CP }} & cp_a);
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assign alu_f = ({8{alu_ctrl_i.alu_op == ALU_OP_ADD}} & add_f) |
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({8{alu_ctrl_i.alu_op == ALU_OP_SUB}} & sub_f) |
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({8{alu_ctrl_i.alu_op == ALU_OP_XOR}} & xor_f) |
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({8{alu_ctrl_i.alu_op == ALU_OP_CP }} & cp_f);
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assign add_a = {1'b0, a_r} + {1'b0, operand_in_i};
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assign add_f = {~(|sub_a[7:0]), 1'b0, 1'b0, sub_a[8], f_r[3:0]}; // TODO: implement H
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assign sub_a = {1'b0, a_r} - {1'b0, operand_in_i};
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assign sub_f = {~(|sub_a[7:0]), 1'b1, 1'b0, sub_a[8], f_r[3:0]}; // TODO: implement H
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assign xor_a = a_r ^ operand_in_i;
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assign xor_f = {~(|xor_a), 3'b0, f_r[3:0]};
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assign cp_a = a_r;
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assign cp_f = sub_f;
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logic [ 7:0] bit_a;
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logic [ 7:0] bit_f;
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assign bsr_a = ({8{alu_ctrl_i.bsr_op.b}} & bit_a);
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assign bsr_f = ({8{alu_ctrl_i.bsr_op.b}} & bit_f);
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assign bit_a = {7'b0, ~operand_in_i[alu_ctrl_i.bsr_op.operand]};
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assign bit_f = {bit_a[0], 2'b10, f_r[4:0]};
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logic [ 7:0] rl_a;
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logic [ 7:0] rl_f;
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assign shift_a = ({8{alu_ctrl_i.shift_op == SHIFT_OP_RL}} & rl_a);
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assign shift_f = ({8{alu_ctrl_i.shift_op == SHIFT_OP_RL}} & rl_f);
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assign rl_a = {operand_in_i[6:0], f_r[4]};
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assign rl_f = {~(|rl_a), 2'b0, operand_in_i[7], f_r[3:0]};
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logic [ 7:0] incdec_input;
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logic [ 7:0] inc_a;
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logic [ 7:0] inc_f;
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logic [ 7:0] dec_a;
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logic [ 7:0] dec_f;
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assign incdec_input = alu_ctrl_i.incdec_op.dst_a ? a_r :
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operand_in_i;
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assign incdec_a = ({8{alu_ctrl_i.incdec_op.inc}} & inc_a) |
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({8{alu_ctrl_i.incdec_op.dec}} & dec_a);
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assign incdec_f = ({8{alu_ctrl_i.incdec_op.inc}} & inc_f) |
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({8{alu_ctrl_i.incdec_op.dec}} & dec_f);
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assign inc_a = incdec_input + 8'h01;
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assign inc_f = {~(|inc_a), 1'b0, inc_a[4], f_r[4], f_r[3:0]};
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assign dec_a = incdec_input - 8'h01;
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assign dec_f = {~(|dec_a), 1'b1, dec_a[4], f_r[4], f_r[3:0]};
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assign operand_out_o = ({8{alu_ctrl_i.shift_op_valid }} & shift_a) |
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({8{alu_ctrl_i.incdec_op_valid}} & incdec_a);
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`include "sva_common.svh"
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`SVA_DEF_CLK(clk);
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`SVA_DEF_NRESET(nreset);
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`SVA_ASSERT_PROP_FATAL(undefined_alu_op,
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tb_top.gb_inst.cpu_inst.instr_valid & alu_ctrl_i.alu_op_valid |-> alu_ctrl_i.alu_op inside {ALU_OP_ADD, ALU_OP_SUB, ALU_OP_XOR, ALU_OP_CP},
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$sformatf("Undefined alu operation pushed: 0x%X", alu_ctrl_i.alu_op)
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);
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`SVA_ASSERT_PROP_FATAL(undefined_shift_op,
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tb_top.gb_inst.cpu_inst.instr_valid & alu_ctrl_i.shift_op_valid |-> alu_ctrl_i.shift_op inside {SHIFT_OP_RL},
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$sformatf("Undefined shift operation pushed: 0x%X", alu_ctrl_i.shift_op)
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);
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`SVA_ASSERT_PROP_FATAL(undefined_bsr_op,
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tb_top.gb_inst.cpu_inst.instr_valid & alu_ctrl_i.bsr_op_valid |-> alu_ctrl_i.bsr_op.b,
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$sformatf("Undefined bsr operation pushed: 0x%X", alu_ctrl_i.bsr_op)
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);
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endmodule : alu
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