283 lines
9.2 KiB
Systemverilog
283 lines
9.2 KiB
Systemverilog
`include "cpu_pkg.svh"
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import cpu_pkg::*;
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module cpu (
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input logic clk,
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input logic nreset,
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output logic [15:0] addr_o,
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input logic [ 7:0] rdata_i,
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output logic we_o,
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output logic [ 7:0] wdata_o
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);
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logic instr_valid;
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logic [ 7:0] instr[2:0];
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logic incr_pc;
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logic pc_we;
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logic [15:0] pc_r;
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logic [15:0] pc_next;
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logic [15:0] pc_bus;
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cc_t ctrl_cc;
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logic ctrl_pc_we;
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logic ctrl_pc_we_cc;
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pc_src_t ctrl_pc_src;
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logic [ 1:0] sp_we;
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logic [15:0] sp_r;
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logic [15:0] sp_next;
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reg8_t reg8_rsel;
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reg8_t reg8_wsel;
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logic reg8_we;
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logic [7:0] reg8_wdata;
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logic [7:0] reg8_rdata;
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reg16_t reg16_sel;
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logic reg16_we;
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logic [15:0] reg16_wdata;
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logic [15:0] reg16_rdata;
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addr_src_t addr_src;
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logic [ 7:0] reg_a;
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logic [ 7:0] reg_f;
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logic alu_update_a;
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logic alu_update_f;
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alu_ctrl_t ctrl_alu_ctrl;
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alu_ctrl_t alu_ctrl;
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logic [ 7:0] alu_operand_in;
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logic [ 7:0] alu_operand_out;
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logic alu16_en;
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logic [15:0] alu16_in;
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logic [15:0] alu16_out;
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logic alu16_inc;
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logic alu16_dec;
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bus_ctrl_t bus_x_ctrl;
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bus_ctrl_t bus_y_ctrl;
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bus16_ctrl_t bus_p_ctrl;
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bus16_ctrl_t bus_q_ctrl;
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logic [ 7:0] bus_x;
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logic [ 7:0] bus_y;
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logic [15:0] bus_p;
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logic [15:0] bus_q;
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logic cc_true;
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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pc_r <= '0;
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else if (pc_we)
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pc_r <= pc_next;
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end
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assign pc_we = ctrl_pc_we | (ctrl_pc_we_cc & cc_true);
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assign pc_next = (ctrl_pc_src == PC_SRC_OPERAND8 ) ? (pc_r + {{8{instr[1][7]}}, instr[1]}) :
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(ctrl_pc_src == PC_SRC_OPERAND16) ? {instr[2], instr[1]} :
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(ctrl_pc_src == PC_SRC_BUS) ? pc_bus :
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pc_r + 16'h01;
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assign cc_true = ((ctrl_cc == CC_NZ) & ~reg_f[7]) |
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((ctrl_cc == CC_Z) & reg_f[7]) |
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((ctrl_cc == CC_NC) & ~reg_f[4]) |
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((ctrl_cc == CC_C) & reg_f[4]);
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assign pc_bus[15:8] = ({8{bus_x_ctrl.dst == BUS_DST_PC_H}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_PC_H}} & bus_y);
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assign pc_bus[ 7:0] = ({8{bus_x_ctrl.dst == BUS_DST_PC_L}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_PC_L}} & bus_y);
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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sp_r[15:8] <= '0;
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else if (sp_we[1])
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sp_r[15:8] <= sp_next[15:8];
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end
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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sp_r[ 7:0] <= '0;
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else if (sp_we[0])
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sp_r[ 7:0] <= sp_next[7:0];
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end
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assign sp_we[1] = instr_valid & (
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(bus_x_ctrl.wen & (bus_x_ctrl.dst == BUS_DST_SP_H)) |
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(bus_y_ctrl.wen & (bus_y_ctrl.dst == BUS_DST_SP_H)) |
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(bus_p_ctrl.wen & (bus_p_ctrl.dst == BUS16_DST_SP)) |
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(bus_q_ctrl.wen & (bus_q_ctrl.dst == BUS16_DST_SP)));
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assign sp_we[0] = instr_valid & (
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(bus_x_ctrl.wen & (bus_x_ctrl.dst == BUS_DST_SP_L)) |
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(bus_y_ctrl.wen & (bus_y_ctrl.dst == BUS_DST_SP_L)) |
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(bus_p_ctrl.wen & (bus_p_ctrl.dst == BUS16_DST_SP)) |
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(bus_q_ctrl.wen & (bus_q_ctrl.dst == BUS16_DST_SP)));
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assign sp_next[15:8] = ({8{bus_x_ctrl.dst == BUS_DST_SP_H}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_SP_H}} & bus_y) |
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({8{bus_p_ctrl.dst == BUS16_DST_SP}} & bus_p[15:8]) |
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({8{bus_q_ctrl.dst == BUS16_DST_SP}} & bus_q[15:8]);
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assign sp_next[ 7:0] = ({8{bus_x_ctrl.dst == BUS_DST_SP_L}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_SP_L}} & bus_y) |
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({8{bus_p_ctrl.dst == BUS16_DST_SP}} & bus_p[ 7:0]) |
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({8{bus_q_ctrl.dst == BUS16_DST_SP}} & bus_q[ 7:0]);
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ctrl ctrl_inst (
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.clk (clk),
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.nreset (nreset),
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.rdata_i (rdata_i),
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.instr_valid_o(instr_valid),
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.instr_o (instr),
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.pc_we_o (ctrl_pc_we),
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.pc_we_cc_o (ctrl_pc_we_cc),
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.pc_src_o (ctrl_pc_src),
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.cc_o (ctrl_cc),
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.reg8_src_o (reg8_rsel),
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.reg8_dest_o (reg8_wsel),
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.reg16_sel_o (reg16_sel),
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.alu_ctrl_o (ctrl_alu_ctrl),
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.addr_src_o (addr_src),
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.alu16_inc_o (alu16_inc),
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.alu16_dec_o (alu16_dec),
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.bus_x_ctrl_o (bus_x_ctrl),
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.bus_y_ctrl_o (bus_y_ctrl),
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.bus_p_ctrl_o (bus_p_ctrl),
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.bus_q_ctrl_o (bus_q_ctrl)
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);
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regbank regbank_inst (
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.clk (clk),
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.nreset (nreset),
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.reg16_wselect_i (reg16_sel),
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.reg16_rselect_i (reg16_sel),
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.reg16_we_i (reg16_we),
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.reg16_wdata_i (reg16_wdata),
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.reg16_rdata_o (reg16_rdata),
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.reg8_wselect_i (reg8_wsel),
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.reg8_we_i (reg8_we),
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.reg8_wdata_i (reg8_wdata),
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.reg8_rselect_i (reg8_rsel),
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.reg8_rdata_o (reg8_rdata)
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);
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assign reg8_we = instr_valid & (
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(bus_x_ctrl.wen & (bus_x_ctrl.dst == BUS_DST_REG8)) |
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(bus_y_ctrl.wen & (bus_y_ctrl.dst == BUS_DST_REG8)));
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assign reg8_wdata = ({8{bus_x_ctrl.dst == BUS_DST_REG8}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_REG8}} & bus_y);
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assign reg16_we =
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instr_valid & (
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(bus_x_ctrl.wen & (bus_x_ctrl.dst == BUS_DST_REG16_H | bus_x_ctrl.dst == BUS_DST_REG16_L)) |
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(bus_y_ctrl.wen & (bus_y_ctrl.dst == BUS_DST_REG16_H | bus_y_ctrl.dst == BUS_DST_REG16_L)) |
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(bus_p_ctrl.wen & (bus_p_ctrl.dst == BUS16_DST_REG16)) |
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(bus_q_ctrl.wen & (bus_q_ctrl.dst == BUS16_DST_REG16)));
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assign reg16_wdata[15:8] = ({8{bus_x_ctrl.dst == BUS_DST_REG16_H}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_REG16_H}} & bus_y) |
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({8{bus_p_ctrl.dst == BUS16_DST_REG16}} & bus_p[15:8]) |
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({8{bus_q_ctrl.dst == BUS16_DST_REG16}} & bus_q[15:8]);
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assign reg16_wdata[ 7:0] = ({8{bus_x_ctrl.dst == BUS_DST_REG16_L}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_REG16_L}} & bus_y) |
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({8{bus_p_ctrl.dst == BUS16_DST_REG16}} & bus_p[ 7:0]) |
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({8{bus_q_ctrl.dst == BUS16_DST_REG16}} & bus_q[ 7:0]);
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alu alu_inst (
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.clk (clk),
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.nreset (nreset),
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.alu_ctrl_i (alu_ctrl),
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.operand_in_i (alu_operand_in),
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.operand_out_o(alu_operand_out),
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.reg_a_o (reg_a),
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.reg_f_o (reg_f)
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);
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always_comb begin
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alu_ctrl = ctrl_alu_ctrl;
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alu_ctrl.update_a = instr_valid & alu_ctrl.update_a;
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alu_ctrl.update_f = instr_valid & alu_ctrl.update_f;
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end
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assign alu_operand_in = ({8{bus_x_ctrl.dst == BUS_DST_ALU}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_ALU}} & bus_y);
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alu16 alu16_inst (
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.operand_in_i (alu16_in),
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.operand_out_o(alu16_out),
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.increment_i (alu16_inc),
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.decrement_i (alu16_dec)
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);
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assign alu16_en = alu16_inc | alu16_dec;
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assign alu16_in = ({16{bus_p_ctrl.dst == BUS16_DST_ALU16}} & bus_p) |
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({16{bus_q_ctrl.dst == BUS16_DST_ALU16}} & bus_q);
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assign addr_o = ({16{addr_src == ADDR_SRC_PC }} & pc_r ) |
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({16{addr_src == ADDR_SRC_SP }} & sp_r ) |
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({16{addr_src == ADDR_SRC_REG16 }} & reg16_rdata) |
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({16{addr_src == ADDR_SRC_REG8 }} & { 8'hFF, reg8_rdata}) |
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({16{addr_src == ADDR_SRC_BUS_P }} & bus_p ) |
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({16{addr_src == ADDR_SRC_BUS_Q }} & bus_q ) |
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({16{addr_src == ADDR_SRC_OPERAND8 }} & { 8'hFF, instr[1] }) |
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({16{addr_src == ADDR_SRC_OPERAND16}} & {instr[2], instr[1] });
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assign we_o = instr_valid & (
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(bus_x_ctrl.wen & bus_x_ctrl.dst == BUS_DST_MEM) |
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(bus_y_ctrl.wen & bus_y_ctrl.dst == BUS_DST_MEM));
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assign wdata_o = ({8{bus_x_ctrl.dst == BUS_DST_MEM}} & bus_x) |
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({8{bus_y_ctrl.dst == BUS_DST_MEM}} & bus_y);
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`define INST_BUS(x) \
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assign bus_``x = ({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_OPERAND8_H)}} & instr[2]) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_OPERAND8_L)}} & instr[1]) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_REG8 )}} & reg8_rdata) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_A )}} & reg_a) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_PC_H )}} & pc_r[15:8]) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_PC_L )}} & pc_r[ 7:0]) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_REG16_H )}} & reg16_rdata[15:8]) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_REG16_L )}} & reg16_rdata[ 7:0]) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_MEM )}} & rdata_i ) | \
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({8{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS_SRC_ALU )}} & alu_operand_out);
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`INST_BUS(x);
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`INST_BUS(y);
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`undef INST_BUS
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`define INST_BUS16(x) \
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assign bus_``x = ({16{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS16_SRC_REG16)}} & reg16_rdata) | \
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({16{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS16_SRC_ALU16)}} & alu16_out ) | \
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({16{bus_``x``_ctrl.wen & (bus_``x``_ctrl.src == BUS16_SRC_SP )}} & sp_r);
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`INST_BUS16(p);
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`INST_BUS16(q);
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`undef INST_BUS16
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endmodule : cpu
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