21 lines
408 B
Systemverilog
21 lines
408 B
Systemverilog
module decode (
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input [7:0] instr0_i,
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input [7:0] instr1_i,
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input [7:0] instr2_i,
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output logic need_instr1_o,
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output logic need_instr2_o,
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output logic undef_o
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);
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logic is_ld_sp_nnnn;
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assign is_ld_sp_nnnn = (instr0_i == 7'h31);
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assign need_instr1_o = is_ld_sp_nnnn;
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assign need_instr2_o = is_ld_sp_nnnn;
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assign undef_o = ~is_ld_sp_nnnn;
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endmodule : decode |