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SystemVerilog 88%
C 11.5%
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Koray Yanik da29d148bf Update synthflow and adapt makefile 2022-02-08 16:14:13 +00:00
build Update synthflow and adapt makefile 2022-02-08 16:14:13 +00:00
rtl Implement push rr 2021-02-23 22:38:10 +00:00
sim Implement LD ($FF00+C), A 2021-02-20 22:10:47 +00:00
synthflow@3f8450ac6a Update synthflow and adapt makefile 2022-02-08 16:14:13 +00:00
.gitignore Implement ld r, r 2021-02-22 21:43:22 +00:00
.gitmodules Initial work on build system 2021-02-15 21:40:12 +00:00
README.md Initial commit 2021-02-15 14:54:08 +01:00

README.md

svgb