fumyuun/svgb
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SystemVerilog 88%
C 11.5%
Makefile 0.5%
e56afb8c9e
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Koray Yanik e56afb8c9e Initial work on build system 
Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
2021-02-15 21:40:12 +00:00
build Initial work on build system 2021-02-15 21:40:12 +00:00
rtl Initial work on build system 2021-02-15 21:40:12 +00:00
sim/tbench Initial work on build system 2021-02-15 21:40:12 +00:00
synthflow@767277e341 Initial work on build system 2021-02-15 21:40:12 +00:00
.gitignore Initial work on build system 2021-02-15 21:40:12 +00:00
.gitmodules Initial work on build system 2021-02-15 21:40:12 +00:00
README.md Initial commit 2021-02-15 14:54:08 +01:00

README.md

svgb