Koray Yanik
e56afb8c9e
Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module.
5 lines
120 B
Makefile
5 lines
120 B
Makefile
TB = tb_top
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SOURCES = gb.sv tb_top.sv
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PATH_SRC = ../rtl:../sim/tbench
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include ../synthflow/vivado/Makefile.rules |