This website requires JavaScript.
Explore
Help
Register
Sign In
fumyuun
/
svgb
Watch
1
Star
0
Fork
You've already forked svgb
0
Code
Issues
Pull Requests
Projects
Releases
Wiki
Activity
e56afb8c9e
svgb
/
rtl
/
gb.sv
9 lines
83 B
Systemverilog
Raw
Blame
History
module
gb
(
input
logic
clk_i
,
input
logic
nreset_i
)
;
endmodule
:
gb
Reference in New Issue
View Git Blame
Copy Permalink